RC48F4400P0VB0EJ NUMONYX, RC48F4400P0VB0EJ Datasheet - Page 59

• Manufacturer Part Number: RC48F4400P0VB0EJ
• Description: IC FLASH 256MBIT 64EZBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of RC48F4400P0VB0EJ

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512M (32Mx16)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-EZBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

P30-65nm
15.4
Table 28: AC Write Specifications
Datasheet
59
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W16
Write to Asynchronous Read Specifications
W18
Write to Synchronous Read Specifications
W19
W20
W28
Write Specifications with Clock Active
W21
W22
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Num
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
(whichever occurs first). Hence, t
Write pulse width high (t
(whichever occurs last). Hence, t
t
V
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
Add 10 ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
This specification must be complied with by customer’s writing timing. The result would be unpredictable if any violation
to this timing specification.
WHVH
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
PHWL
ELWL
WLWH
DVWH
AVWH
WHEH
WHDX
WHAX
WHWL
VPWH
QVVL
QVBL
BHWH
WHGL
WHQV
WHAV
WHCH/L
WHVH
WHVL
VHWL
CHWL
Symbol
and WP# should be at a valid level until erase or program success is determined.
or t
AC Write Specifications
WHCH/L
RST# high recovery to WE# low
CE# setup to WE# low
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
V
V
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
WE# high to read valid
WE# high to Address valid
WE# high to Clock valid
WE# high to ADV# high
WE# high to ADV# low
ADV# high to WE# low
Clock high to WE# low
must be met when transiting from a write cycle to a synchronous burst read.
PP
PP
setup to WE# high
hold from Status read
WLWH
WHWL
or t
or t
ELEH
WHWL
WLWH
EHEL
Parameter
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
= t
= t
EHEL
ELEH
= t
= t
WHEL
WLEH
= t
= t
EHWL
ELWH
).
.
t
AVQV
Min
150
200
200
50
50
50
20
19
19
0
0
0
0
0
0
0
0
7
-
-
+ 35
Max
20
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Order Number: 320002-10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3,6,10
1,2,3,6,10
1,2,3,6,8
1,2,3,11
1, 2, 12
1,2,3,7
1,2,3,7
Notes
1,2,3
1,2,3
1,2,4
1,2,5
1,2,9
Mar 2010
1,2