AT45DB642D-TU Atmel, AT45DB642D-TU Datasheet - Page 21

IC FLASH 64MBIT 66MHZ 28TSOP

AT45DB642D-TU

Manufacturer Part Number
AT45DB642D-TU
Description
IC FLASH 64MBIT 66MHZ 28TSOP
Manufacturer
Atmel
Datasheet

Specifications of AT45DB642D-TU

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
64M (8192 pages x 1056 bytes)
Speed
66MHz
Interface
Parallel/Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSOP
Density
64Mb
Access Time (max)
6ns
Interface Type
Parallel/Serial-SPI
Boot Type
Not Required
Address Bus
1/8Bit
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP-I
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
8M
Supply Current
15mA
Mounting
Surface Mount
Pin Count
28
Data Bus Width
8 bit
Architecture
Sectored
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
15 mA
Mounting Style
SMD/SMT
Organization
256 KB x 32
Memory Configuration
8192 Pages X 1056 Bytes
Clock Frequency
66MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
TSOP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Figure 10-3. Program Security Register
10.2.2
Figure 10-4. Read Security Register
3542K–DFLASH–04/09
SO or IO
SI or IO
SI or IO
Reading the Security Register
7
7
- IO
- IO
CS
7
- IO
CS
0
0
0
Each transition
represents 8 bits
Each transition
represents 8 bits
The Security Register can be read by first asserting the CS pin and then clocking in an opcode
of 77H followed by three dummy bytes if using the serial interface and seven dummy bytes if
using the 8-bit interface. After the last don't care bit has been clocked in, the content of the
Security Register can be clocked out on the SO or I/O7 - I/O0 pins. After the last byte of the
Security Register has been read, additional pulses on the SCK/CLK pin will simply result in
undefined data being output on the SO or I/O7 - I/O0 pins.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO or
I/O7 - I/O0 pins into a high-impedance state.
Opcode
Opcode
Byte 1
Opcode
Byte 2
X
Opcode
Byte 3
X
Opcode
Byte 4
X
Data Byte
n
Data Byte
n
Data Byte
n + 1
Data Byte
n + 1
Data Byte
n + x
Data Byte
n + x
21

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