AT45DB161D-TU Atmel, AT45DB161D-TU Datasheet
AT45DB161D-TU
Specifications of AT45DB161D-TU
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AT45DB161D-TU Summary of contents
Page 1
... Its 17,301,504-bits of memory are organized as 4,096 pages of 512-bytes or 528-bytes each. In addition to the main memory, the AT45DB161D also contains two SRAM buffers of 512-/528-bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream ...
Page 2
... The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB161D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). ...
Page 3
... Ground: The ground reference for the power supply. GND should be connected to the system GND ground. 3500N–DFLASH–05/10 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. CC Atmel AT45DB161D Asserte d State Type Low Input – Input – ...
Page 4
... BLOCK 2 BLOCK 30 BLOCK 31 BLOCK 32 BLOCK 33 BLOCK 62 BLOCK 63 BLOCK 64 BLOCK 65 BLOCK 510 BLOCK 511 Block = 4,096-/4,224-bytes BUFFER 2 (512-/528-BYTES) SO ® AT45DB161D is divided into three levels of PAGE ARCHITECTURE 8 Pages PAGE 0 PAGE 1 PAGE 6 PAGE 7 PAGE 8 PAGE 9 PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18 PAGE 4,094 ...
Page 5
... Table 15-1 on page 27 through Table 15-7 on page ® DataFlash page size (528-bytes) is referenced in the datasheet using the ™ protocols for Mode 0 and Mode 3. Please refer to the Atmel AT45DB161D 30. A valid instruction 5 ...
Page 6
... A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. Atmel AT45DB161D perform a continuous read array with the CAR1 ...
Page 7
... CS pin will terminate the read operation and tri-state the output pin (SO). 3500N–DFLASH–05/10 ® DataFlash page size (528-bytes), an opcode of D2H must be clocked into the specification. The Main Memory Page Read bypasses both data buffers SCK . The D1H and D3H opcode can be used for lower CAR1 . CAR2 Atmel AT45DB161D 7 ...
Page 8
... PA0) that specify the page in the main memory to be erased and 10 don’t care bits. To perform a page erase in the binary page size (512-bytes), the opcode 81H must be loaded into the device, followed by three address bytes consist of three don’t care bits, 12 Atmel AT45DB161D 8 ® ...
Page 9
... Atmel AT45DB161D . During this time, the PE . During this time, the status register and the BE PA4/ PA3/ PA2/ PA1/ A13 A12 A11 A10 • • • • • • • ...
Page 10
... Chip Erase Figure 7-1. Chip Erase CS Opcode SI Byte 1 Each transition represents eight bits Note: 1. Refer to the errata regarding Chip Erase on Atmel AT45DB161D 10 . During this time, the status register and the RDY/BUSY pin will indicate that SE PA8/ PA7/ PA6/ PA5/ PA4/ A17 A16 ...
Page 11
... Table 8-1. Enable Sector Protection Command Command Enable Sector Protection Figure 8-1. Enable Sector Protection CS Opcode SI Byte 1 Each transition represents eight bits 3500N–DFLASH–05/10 Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Byte 2 Byte 3 Byte 4 Atmel AT45DB161D Byte 3 Byte 4 7FH A9H 11 ...
Page 12
... In this case, the Disable Sector Protection command would need to be issued while the WP pin is deasserted to disable the sector protection. The Disable Sector Protection command is also ignored whenever the WP pin is asserted. A noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the WP pin. Atmel AT45DB161D 12 Byte 1 Byte 2 3DH ...
Page 13
... Issue Command X – Issue Command illustrates the format of the Sector Protection Register.: 0 (0a, 0b) See Table 9-3 (Page 0-7) Bit 7, 6 (1) Atmel AT45DB161D 3 Sector Disable Sector Protection Protection Command Status X Disabled Issue Command Disabled – Enabled X Enabled ...
Page 14
... If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed. For example, if only the first two bytes are clocked in instead of the complete 16-bytes, then the protection status of the last 14 sectors cannot be Atmel AT45DB161D 14 Byte 1 ...
Page 15
... Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Byte 1 Byte 2 32H xxH Data Byte Atmel AT45DB161D Byte 3 Byte 4 7FH FCH Data Byte Data Byte Byte 3 Byte 4 xxH xxH Data Byte Data Byte byte will be ...
Page 16
... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown command if necessary. Table 10-1. Sector Lockdown Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents eight bits Atmel AT45DB161D 16 Byte 1 Byte 2 3DH 2AH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 ...
Page 17
... See Below 0a 0b (Page 0-7) (Page 8-255) Bit 7, 6 Bit Byte 1 Byte 2 35H xxH Data Byte n Atmel AT45DB161D FFH 00H Data Value Bit 3, 2 Bit 00H 00 00 C0H 00 00 30H 00 00 F0H Byte 3 Byte 4 xxH xxH Data Byte Data Byte ...
Page 18
... The Program Security Register command utilizes the internal SRAM buffer 1 for processing. Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents eight bits Atmel AT45DB161D 18 Security Register Byte Number 1 · · · Factory Programmed By Atmel ...
Page 19
... On completion of the compare operation, bit six of the status register is updated with the result of the compare. 3500N–DFLASH–05/ ® page size (528-bytes), a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must COMP Atmel AT45DB161D Data Byte Data Byte Data Byte the status register can be read or XFR ...
Page 20
... Bit zero in the Status Register indicates whether the page size of the main memory array is configured for “power of 2” binary page size (512-bytes) or standard DataFlash page size (528-bytes). If bit zero is a one, then the page size is set to 512-bytes. If bit zero is a zero, then the page size is set to 528-bytes. Atmel AT45DB161D 20 ® ...
Page 21
... The device density is indicated using bits five, four, three, and two of the status register. For the Atmel AT45DB161D, the four bits are 1011 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of Atmel DataFlash devices. The device density is not the same as the density code indicated in the JEDEC device ID information ...
Page 22
... Power of Two Page Size Figure 13-1. Erase Sector Protection Register CS Opcode SI Byte 1 Each transition represents eight bits Atmel AT45DB161D 22 Section 26. “Ordering Information” on page 13.1). , during which time the Status Register will indicate that the device is busy. The P Byte 1 3DH Opcode ...
Page 23
... Byte 3 Device Device Information Information String Length Byte x This information would only be output if the Extended Device Information String Length value was something other than 00H. Atmel AT45DB161D Bit 0 1 Manufacturer ID 1FH = Atmel Family Code 001 = Atmel DataFlash Bit 0 0 Density Code ...
Page 24
... However, during the internally self-timed portion of Group B commands, any command in Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self-timed portion of a Group D command, only the Status Register Read command should be executed. Atmel AT45DB161D 24 3500N–DFLASH–05/10 ...
Page 25
... Disable Sector Protection Erase Sector Protection Register Program Sector Protection Register Read Sector Protection Register Sector Lockdown Read Sector Lockdown Register Program Security Register Read Security Register 3500N–DFLASH–05/10 Atmel AT45DB161D Opcode D2H E8H 03H 0BH D1H D3H D4H D6H ...
Page 26
... Command Buffer 1 Read Buffer 2 Read Main Memory Page Read Continuous Array Read (2) Status Register Read Notes: 1. These legacy commands are not recommended for new designs 2. Refer to the Revision History table on Atmel AT45DB161D 26 (1) page 52 Opcode 53H 55H 60H 61H 58H 59H ...
Page 27
... E8h Notes Don’t Care 3500N–DFLASH–05/10 Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Atmel AT45DB161D Address Byte N/A N Additional Don’t Care Bytes N/A N N/A N/A N N N/A ...
Page 28
... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Page Address Bit B = Byte/Buffer Address Bit Atmel AT45DB161D 28 Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Don’t Care ...
Page 29
... An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption. 3500N–DFLASH–05/10 Atmel AT45DB161D ). At this time, all operations are disabled and the device does not POR ...
Page 30
... Voltage Extremes referenced in the "Absolute Maximum Ratings" are intended to accommodate short duration undershoot/overshoot condi- + 0.6V CC tions and does not imply or guarantee functional device operation at these levels for any extended period of time Atmel AT45DB161D (2.5V Version) -40C to 85C 2.5V to 3.6V Condition CS, RESET all IH ...
Page 31
... Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC Note: 1. Values are based on device characterization, not 100% tested in production 3500N–DFLASH–05/10 Atmel AT45DB161D Atmel AT45DB161D (2.5V Version) Atmel AT45DB161D Min Typ Max Min 6.8 6.8 6.8 6.8 0.1 0.1 ...
Page 32
... RapidS serial case. 21.1 Waveform 1 – SPI Mode 0 Compatible (for frequencies up to 66MHz CSS SCK HIGH IMPEDANCE VALID IN Atmel AT45DB161D 32 AC 1.5V MEASUREMENT LEVEL page 36. Waveform 1 shows the SCK signal being low when CS ® RapidS serial interface but for frequencies up to 66MHz ...
Page 33
... HO VALID OUT 66MHz) MAX CSH VALID OUT 66MHz) MAX CSH VALID OUT t H ® ™ RapidS function's ability to operate at higher clock frequencies, a full clock cycle Atmel AT45DB161D DIS HIGH IMPEDANCE CS DIS HIGH IMPEDANCE t CS DIS HIGH IMPEDANCE ® is designed to always 33 ...
Page 34
... G. Master clocks in first bit of BYTE-SO H. Slave clocks out second bit of BYTE-SO I. Master clocks in last bit of BYTE-SO 21.6 Reset Timing CS SCK RESET HIGH IMPEDANCE SO (OUTPUT) SI (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted Atmel AT45DB161D LSB BYTE-MOSI ...
Page 35
... Page Address Byte/Buffer Address (A20 - A9) (A8 - A0/BFA8 - BFA0) CMD 8-bits 8-bits 8-bits Page Address Bits (PA11 - PA0) (BA9 - BA0/BFA9 - BFA0) FLASH MEMORY ARRAY BUFFER 2 (512-/528-BYTES) I/O INTERFACE SI Atmel AT45DB161D LSB LSB Byte/Buffer Address BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 2 WRITE 35 ...
Page 36
... The following block diagram and waveforms illustrate the various read sequences available. FLASH MEMORY ARRAY PAGE (512-/528-BYTES) MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (512-/528-BYTES) BUFFER 1 READ Atmel AT45DB161D 36 BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 X CMD X···X, BFA9-8 BFA7-0 Starts self-timed erase/program operation ...
Page 37
... BA7-0 CMD A20- DON'T CARE BITS CMD PA11-6 BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 CMD X X..X, BFA9-8 Each transition represents eights bits Atmel AT45DB161D Dummy Bytes n n+1 Starts reading page data into buffer BINARY PAGE SIZE PA5-0, XX XXXX XXXX BFA7 Dummy Byte (opcodes D1H and D3H) ...
Page 38
... Continuous Array Read (Legacy Opcode E8H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.2 Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO 24.3 Continuous Array Read (Low Frequency: Opcode 03H SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT45DB161D ADDRESS BITS MSB ADDRESS BITS A20 - MSB ...
Page 39
... BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD ATMEL DATAFLASH PAGE SIZE = 14 DON'T CARE + BFA9-BFA0 MSB ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD ATMEL DATAFLASH PAGE SIZE = 14 DON'T CARE + BFA9-BFA0 MSB Atmel AT45DB161D DON'T CARE BITS MSB DATA BYTE MSB DON'T CARE ...
Page 40
... Read Sector Protection Register (Opcode 32H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.9 Read Security Register (Opcode 77H SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT45DB161D DON'T CARE MSB DON'T CARE MSB DON'T CARE ...
Page 41
... Manufacturer and Device Read (Opcode 9FH SCK OPCODE SI 9FH HIGH-IMPEDANCE SO Note: Each transition 3500N–DFLASH–05/ STATUS REGISTER DATA MSB MSB 1FH DEVICE ID BYTE 1 DEVICE ID BYTE 2 shown for SI and SO represents one byte (8-bits) Atmel AT45DB161D STATUS REGISTER DATA MSB 00H 41 ...
Page 42
... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array Atmel AT45DB161D 42 START provide address ...
Page 43
... MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER END Atmel AT45DB161D If planning to modify multiple bytes currently stored within a page of the Flash array 43 ...
Page 44
... AT45DB161D-SU-SL954 (4) AT45DB161D-SU-SL955 AT45DB161D-TU AT45DB161D-MU-2.5 AT45DB161D-SU-2.5 AT45DB161D-TU-2.5 AT45DB161D-CU Notes: 1. The shipping carrier option is not marked on the devices 2. Standard parts are shipped with the page size set to 528-bytes. The user is able to configure these parts to a 512- byte page size if desired 3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 512-bytes. Parts will have a 954 or SL954 marked on them 4 ...
Page 45
... Package Drawing Contact: packagedrawings@atmel.com 3500N–DFLASH–05/ Pin 0.45 (0. TITLE 8M1-A, 8-pad 1.00mm Body, Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN) Atmel AT45DB161D SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A – 0.85 1.00 A1 – – ...
Page 46
... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com Atmel AT45DB161D TOP VIEW ...
Page 47
... Package Drawing Contact: packagedrawings@atmel.com 3500N–DFLASH–05/10 PIN 1 0º ~ 5º SEATING PLANE A1 SYMBOL TITLE 28T, 28-lead (8 x 13.4mm) Plastic Thin Small Outline Package, Type I (TSOP) Atmel AT45DB161D GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX NOM NOTE A – – 1. ...
Page 48
... Ball Grid Array Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 1.00 (0.039) REF 1.00 (0.0394) BSC NON-ACCUMULATIVE 1.00 (0.0394) BSC NON-ACCUMULATIVE Package Drawing Contact: packagedrawings@atmel.com Atmel AT45DB161D 48 6.10(0.240) 5.90(0.232 8.10(0.319) 7.90(0.311) TOP VIEW 1.40 (0.055) MAX 4.0 (0.157 BOTTOM VIEW TITLE 24C1, 24-ball ( Array ...
Page 49
... Added “Legacy Commands” table Added 2.5V - 3.6V operating range Changed t from 30µs to 50µs min VCSL Changed t from 10ms to 20ms max PUW Changed t from 8ns to 6ns max (2.7V device) DIS Changed t from 8ns to 6ns max (2.7V device) V Initial Document Release Atmel AT45DB161D 49 ...
Page 50
... Errata 29.1 No Errata Conditions Atmel AT45DB161D 50 3500N–DFLASH–05/10 ...
Page 51
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...