MT28F128J3RG-12 ET TR Micron Technology Inc, MT28F128J3RG-12 ET TR Datasheet - Page 36
![IC FLASH 128MBIT 120NS 56TSOP](/photos/7/30/73003/mfg557-56-tsop_sml.jpg)
MT28F128J3RG-12 ET TR
Manufacturer Part Number
MT28F128J3RG-12 ET TR
Description
IC FLASH 128MBIT 120NS 56TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT28F128J3FS-12_ET_TR.pdf
(55 pages)
Specifications of MT28F128J3RG-12 ET TR
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16Mx8, 8Mx16)
Speed
120ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
56-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1001-2
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
Figure 14: SET BLOCK LOCK BITS
FULL STATUS CHECK PROCEDURE
SET BLOCK LOCK BITs
SET BLOCK LOCK BITS
Read Status Register
Data (see above)
Check if Desired
Block Address
Block Address
Read Status
Full Status
Write 60h,
Write 01h,
Complete
Successful
Register
SR4,5 =
SR3 =
SR7 =
SR4 =
Start
1
0
0
0
Flowchart
0
1
1
1
SET BLOCK LOCK BITS
Command Sequence
Voltage Range Error
Error
Error
36
BUS
OPERATION
WRITE
WRITE
READ
STANDBY
Repeat for subsequent lock bit operations.
Full status check can be done after each lock bit set operation or
after a sequence of lock bit set operations.
Write FFh after the last lock bit set operation to place device in read
array mode.
BUS
OPERATION
STANDBY
STANDBY
STANDBY
SR5, SR4, and SR3 are only cleared by the Clear Status Register
command in cases where multiple lock bits are set before full
status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COMMAND
COMMAND
SET BLOCK
LOCK BITS
SETUP
SET BLOCK
LOCK BITS
CONFIRM
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
COMMENTS
Check SR3
1= Programming Voltage
Check SR4, SR5
Both 1 = Command
Check SR4
1 = Set Block Lock Bits Error
COMMENTS
Data = 60h
Addr = Block Address
Data = 01h
Addr = Block Address
Status Register Data
Check SR7
1 = ISM Ready
0 = ISM Busy
Error Detect
Sequence Error
©2000 Micron Technology. Inc.