MT47H32M16BN-25E IT:D TR Micron Technology Inc, MT47H32M16BN-25E IT:D TR Datasheet - Page 18
MT47H32M16BN-25E IT:D TR
Manufacturer Part Number
MT47H32M16BN-25E IT:D TR
Description
IC DDR2 SDRAM 512MBIT 84FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Specifications of MT47H32M16BN-25E IT:D TR
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (32Mx16)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
84-FBGA
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
295mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued)
PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
G8, G2, H7,
H3, H1, H9,
C2, D7, D3,
D1, D9, B1,
F1, F9, C8,
K7, L7, K3
Number
x16 Ball
F3, B3
F7, E8
K9
B9
L8
–
–
–
x4, x8 Ball
D3, D1, D9,
C8, C2, D7,
C8, C2, D7,
F7, G7, F3
Number
B1, B9
B7, A8
G8
D3
B3
F9
–
–
LDQS, LDQS#
DQ12–DQ14,
RAS#, CAS#,
LDM, UDM,
DQ9–DQ11,
DQS, DQS#
DQ0–DQ2,
DQ3–DQ5,
DQ6–DQ8,
DQ0–DQ2,
DQ3–DQ5,
DQ0–DQ2,
DQ6, DQ7
Symbol
DQ15
WE#
ODT
DQ3
CS#
DM
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
I/O
Description
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS#
is registered high. CS# provides for external bank selection on sys-
tems with multiple ranks. CS# is considered part of the command
code.
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of DQS.
Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls. LDM is DM for lower byte DQ0–
DQ7 and UDM is DM for upper byte DQ8–DQ15.
On-die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ15, LDM, UDM,
LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7, DQS,
DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#,
and DM for the x4. The ODT input will be ignored if disabled via
the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Data input/output: Bidirectional data bus for 32 Meg x 16.
Data input/output: Bidirectional data bus for 64 Meg x 8.
Data input/output: Bidirectional data bus for 128 Meg x 4.
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data, center-
aligned with write data. DQS# is only used when differential data
strobe mode is enabled via the LOAD MODE command.
Data strobe for lower byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. LDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE com-
mand.
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
512Mb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.