MT45W1MW16BDGB-701 WT TR Micron Technology Inc, MT45W1MW16BDGB-701 WT TR Datasheet
MT45W1MW16BDGB-701 WT TR
Specifications of MT45W1MW16BDGB-701 WT TR
MT45W1MW16BDGB-701 WT TR
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MT45W1MW16BDGB-701 WT TR Summary of contents
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... DQ15 A19 A12 A13 WE# H A18 A8 A9 A10 A11 J WAIT CLK ADV Top View (Ball Down) Designator Workgroup 1.0 specifications. 2. Contact factory. Part Number Example: MT45W1MW16BDGB-701WT ©2005 Micron Technology, Inc. All rights reserved. Features 6 CRE DQ0 DQ2 DQ6 DQ7 NC NC None ...
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... Timing Requirements .33 Timing Diagrams .37 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Revision History .58 PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23zTOC.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2005 Micron Technology, Inc. All rights reserved. ...
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... Figure 46: Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Figure 47: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23zLOF.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TCR Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ©2005 Micron Technology, Inc. All rights reserved. ...
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... Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Table 16: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23zLOT.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2005 Micron Technology, Inc. All rights reserved. ...
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... General Description Micron low-power, portable applications. The MT45W1MW16BDGB is a 16Mb DRAM core device organized as 1 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans- parent self-refresh mechanism ...
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... LB# UB# Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Address Decode 1,024K x 16 Logic DRAM MEMORY ARRAY ...
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... Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower byte enable: DQ[7:0]. Upper byte enable: DQ[15:8]. ...
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... When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence rent. 7. DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 CLK ADV# CE# OE# WE ...
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... To view the location of the abbreviated mark on the device, refer to customer service note, CSN-11, “Product Mark/Label” at www.micron.com/csn. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory BD GB -70 8 www.micron.com/partsearch Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Functional Description In general, the MT45W1MW16BDGB devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W1MW16BDGB contains a 16,777,216-bit DRAM core organized as 1,048,576 addresses by 16 bits. This device implements the same high-speed bus interface found on burst mode Flash products. ...
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... Page mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode read accesses. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory ADDRESS VALID DATA VALID READ Cycle Time t < ...
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... CellularRAM device. The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to indicate when data transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses the boundary between 128-word rows. Once the Cellu- larRAM device has restored the previous row’ ...
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... Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory CEM unless row boundaries are crossed at least every VALID Latency Code 2 (3 clocks) ...
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... LOW) Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID Latency Code 2 (3 clocks) D[0] 14 Bus Operating Modes D[1] ...
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... CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges ...
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... Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 Bus Operating Modes ...
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... Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 Bus Operating Modes ...
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... Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 6 on page 28) ...
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... WRITE operation when the configuration register enable (CRE) input is HIGH (see Figure 13 on page 19 and Figure 14 on page 20). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are placed on address pins A[19:0 asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first ...
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... WAIT cycles caused by refresh collisions require a corresponding number of addi- tional CE# LOW cycles. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Latch Control Register Address t CBPH High-Z Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... OE# WE# LB#/UB# DATA Note: If the data present when WE# falls is not 0000h or 0001h possible that the maximum address will be overwritten. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory READ READ ADDRESS ADDRESS (MAX) (MAX) XXXXh XXXXh Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... OE# WE# LB#/UB# DATA Note: If the data present when WE# falls is not 0000h or 0001h possible that the maximum address will be overwritten. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory READ READ ADDRESS ADDRESS (MAX) (MAX) XXXXh XXXXh Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. The BCR is accessed using CRE and A[19] HIGH or through the configuration register software sequence with DQ = 0001h on the third cycle ...
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... PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 8-Word Burst Length 16-Word Burst length ...
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... The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option should be more than adequate in stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced- drive-strength option is included to minimize noise generated on the data bus during READ operations ...
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... V IH ADV DQ[15: DQ[15: PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory D[1] D[0] 104 MHz 66 (15ns) 104 (9.62ns) Code 2 VALID OUTPUT Code 3 (Default) 26 Configuration Registers BCR[ Data valid in current cycle. BCR[ Data valid in next cycle. ...
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... Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array ...
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... The page mode operation bit determines whether page mode is enabled for asynchro- nous READ operations. In the power-up default state, page mode is disabled. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Active Section Address Space Full die 000000h– ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Parameter , V Q relative CC CC ...
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... V slightly higher for up to 500ms after power-up, after changes to the PAR array partition, or when entering standby mode. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 (–30ºC < T < +85ºC); Industrial temperature (–40ºC < ...
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... Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W1MW16BDGB device. The typical values shown in Figure 23 are measured with the default on-chip temperature sensor control enabled. The maximum values shown in Table 9 are measured with the relevant TCR bits set in the configuration register. ...
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... Output timing ends at V Figure 25: Output Load Circuit DUT Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Conditions 0V; +25° Conditions Symbol T = +25º ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low- Z timings measure a 100mV transition away from the High Page mode enabled only. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 Timing Requirements ...
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... High-Z timings measure a 100mV transition from either V 4. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low- Z timings measure a 100mV transition away from the High PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 104 MHz Symbol Min t ABA t ...
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... OH 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The High-Z timings measure a 100mV transition from either V 3. WE# LOW time must be limited to PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory CEM (8µs). ...
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... CE# HIGH CE# HIGH for greater than 15ns. Figure 26: Initialization Period Vcc, VccQ = 1.7V Table 16: Initialization Timing Parameters Parameter Initialization period (required before normal operations) PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 104 MHz Symbol Min t CBPH 5 t CEM t ...
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... Timing Diagrams Figure 27: Asynchronous READ A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS OLZ BLZ High CEW V OH High DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Figure 28: Asynchronous READ Using ADV# A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS VPH t AVS t AVH AADV CVS OLZ V t BLZ High CEW V OH High DON’T CARE Micron Technology, Inc ...
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... Figure 29: Page Mode READ A[19:4] A[3:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS VALID VALID ADDRESS V ADDRESS CEM OLZ BLZ t APA VALID High-Z OUTPUT CEW V OH High Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... V OL READ Burst Identified (WE# = HIGH) Notes: 1. Non-default BCR settings for single-access burst READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CEM t t ...
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... HIGH) Note: Non-default BCR settings for 4-word burst READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t KHKL t CLK t CEM t ABA t BOE ...
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... DQ[15:0] High ACLK Note: Non-default BCR settings for READ burst suspend: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CEM t OHZ t BOE t KOH ...
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... WAIT will be asserted a maximum of (2 × LC) cycles (BCR[ WAIT asserted during delay latency code (BCR[13:11]). 3. CE# must not remain LOW longer than PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Note 3 t KHTL Note 2 VALID OUTPUT t CEM ...
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... Figure 34: CE#-Controlled Asynchronous WRITE A[19:0] ADV# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS CE WPH High WHZ CEW V OH High Timing Diagrams CPH VALID INPUT t HZ High-Z DON’ ...
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... Figure 35: LB#/UB#-Controlled Asynchronous WRITE A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS WPH High WHZ CEW V OH High Timing Diagrams VALID INPUT t HZ High-Z DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Figure 36: WE#-Controlled Asynchronous WRITE A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS WPH High WHZ CEW V OH High Timing Diagrams VALID INPUT High-Z DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... Figure 37: Asynchronous WRITE Using ADV# A[19:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT WAIT PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS AVH t AVS VPH High WHZ CEW V OH High Timing Diagrams t WPH t WP ...
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... V IL WRITE Burst Identified (WE# = LOW) Note: Non-default BCR settings for burst WRITE operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CEM t KHTL D[0] Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... WAIT asserts. This differ- ence in behavior will not be noticed by controllers that monitor WAIT, or that use WAIT to abort on the start-of-row input cycle. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Note 4 t KHTL Note 3 VALID INPUT ...
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... CE# HIGH CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE clocked HIGH to terminate the burst. 3. Clock rates below 50 MHz ( PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t SP VALID ADDRESS ...
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... CE# HIGH CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE clocked HIGH to terminate the burst. 3. Clock rates below 50 MHz ( PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CKA VALID ...
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... CE# HIGH CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE clocked HIGH to terminate the burst. 3. Clock rates below 50 MHz ( PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CKA VALID ...
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... When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: a) clocked CE# HIGH CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE clocked HIGH to terminate the burst. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK ...
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... When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: a) clocked CE# HIGH CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE clocked HIGH to terminate the burst. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK ...
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... IH High-Z DATA IN/OUT Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( required after CE#-controlled WRITEs. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS CPH High-Z DATA CPH) to schedule the appropriate internal refresh operation. Otherwise, Micron Technology, Inc ...
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... WAIT DQ[15:0] IN/OUT Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns ( required after CE#-controlled WRITEs. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS VALID ADDRESS AVS t AVH ...
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... All dimensions in millimeters; MAX/MIN or typical, as noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W1MW16BDGB uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc ...
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... Changed file name to new standard: p23z16_b_cr1-0 to 16mb_burst_cr1_0_p23z Rev .10/05 • Fixed exceptions to template (primarily minor formatting on page 1) PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table 16 on page 36 from a MIN to a MAX value CW” to “ ...
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... Rev .08/05 • Initial release with “Advance” designation. PDF: 09005aef81cb58ed/Source: 09005aef81c7a667 16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN 16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 59 Revision History ©2005 Micron Technology, Inc. All rights reserved. ...