CY7C1338B-100AC Cypress Semiconductor Corp, CY7C1338B-100AC Datasheet - Page 3

• Manufacturer Part Number: CY7C1338B-100AC
• Description: IC SRAM 4MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1338B-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1091

Pin Configurations
Pin Descriptions
Document #: 38-05143 Rev. **
ADSC
ADSP
A
A
BW
ADV
BWE
GW
CLK
CE
Name
[1:0]
[16:2]
1
[3:0]
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
I/O
(continued)
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
captured in the address registers. A
ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
captured in the address registers. A
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
A
used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A
at the rising edge of the CLK, if CE
LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
rising edge. BW
and DP
Advance Input used to advance the on-chip address counter. When LOW the internal burst counter
is advanced in a burst sequence. The burst sequence is selected using the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
a global write, independent of the state of BWE and BW
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
A
B
C
D
G
H
K
M
N
R
U
E
F
L
P
T
J
1
, A
0
Address Inputs. These inputs feed the on-chip burst counter as the LSBs as well as being
2
3
V
V
V
V
V
, and BW
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
to select/deselect the device. CE
NC
NC
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
1
d
d
d
d
c
c
c
c
0
controls DQ
3
controls DQ
TMS
DQ
DQ
DQ
DQ
CE
DQ
DQ
DQ
DQ
V
NC
NC
NC
A
A
A
2
DD
2
c
c
c
c
d
d
d
d
CY7C1338B (128K x 32)
119-Ball BGA
MODE
[7:0]
BW
BW
V
V
V
V
V
V
V
V
TDI
NC
[31:24]
3
A
A
A
A
SS
SS
SS
SS
SS
SS
SS
SS
and DP
c
d
1
, CE
[1:0]
[1:0]
and DP
2
ADSP
ADSC
are also loaded into the burst counter. When ADSP and
are also loaded into the burst counter. When ADSP and
, and CE
BWE
ADV
CLK
TCK
V
CE
GW
V
V
0
NC
OE
NC
A1
A0
[1:0]
A
, BW
4
DD
DD
DD
1
Description
gates ADSP.
1
3
. See Write Cycle Descriptions table for further details.
to select one of the 64K address locations. Sampled
1
3
controls DQ
are sampled active, and ADSP or ADSC is active
TDO
BW
BW
V
V
V
V
V
V
V
V
V
NC
A
A
A
A
5
SS
SS
SS
SS
SS
SS
SS
SS
DD
a
b
[3:0]
. Global writes override byte writes.
[15:8]
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
NC
NC
NC
NC
NC
A
A
A
6
DD
b
b
b
b
a
a
a
a
and DP
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
NC
NC
1
DDQ
DDQ
DDQ
DDQ
ZZ
DDQ
7
, BW
b
b
b
b
a
a
a
a
1
is deasserted HIGH.
2
CY7C1338B
controls DQ
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