CY7C1338B-100AC Cypress Semiconductor Corp, CY7C1338B-100AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1338B-100AC
• Description: IC SRAM 4MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1338B-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1091

data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the RAM
core. The information presented to DQ
the specified address location. Byte writes are allowed. During
byte writes, BW
controls DQ
three-stated when a write is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be three-stated prior to
the presentation of data to DQ
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Burst Sequences
The CY7C1338B provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to an interleaved
burst sequence.
ZZ Mode Electrical Characteristics
Document #: 38-05143 Rev. **
I
t
t
CCZZ
ZZS
ZZREC
Parameter
[23:16]
0
controls DQ
, and BWS
Device operation to
ZZ recovery time
standby current
Snooze mode
Description
1
3
[7:0]
[31:0]
, CE
ZZ
controls DQ
, BW
. As a safety precaution, the
2
, and CE
1
[31:0]
controls DQ
[31:24]
will be written into
3
Test Conditions
ZZ > V
ZZ > V
are all asserted
ZZ < 0.2V
. All I/Os are
[15:8]
DD
DD
, BW
0.2V
0.2V
[3:0]
[1:0]
2
)
,
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
Table 2. Counter Implementation for a Linear Sequence
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. CE
inactive for the duration of t
LOW. Leaving ZZ unconnected defaults the device into an ac-
tive state.
Address
A
Address
A
X + 1
X + 1
First
First
2t
Min.
00
01
10
00
01
10
11
11
CYC
, A
, A
x
x
1
, CE
Address
A
Address
A
Second
Second
X + 1
X + 1
01
00
10
01
10
00
11
11
2
, CE
, A
, A
2t
x
x
Max.
3
10
ZZREC
CYC
, ADSP, and ADSC must remain
Address
Address
A
A
after the ZZ input returns
Third
X + 1
Third
X + 1
10
11
00
01
10
11
00
01
, A
, A
CY7C1338B
x
x
Page 5 of 18
Unit
mA
Address
Address
A
ns
ns
A
Fourth
Fourth
X + 1
X + 1
11
10
01
00
11
00
01
10
, A
, A
x
x