CY7C1338B-100AC Cypress Semiconductor Corp, CY7C1338B-100AC Datasheet - Page 9

• Manufacturer Part Number: CY7C1338B-100AC
• Description: IC SRAM 4MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1338B-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1091

Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Document #: 38-05143 Rev. **
OUTPUT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
C
C
10. t
12. This parameter is sampled and not 100% tested.
11. At any given voltage and temperature, t
CYC
CH
CL
AS
AH
CDV
DOH
ADS
ADH
WES
WEH
ADVS
ADVH
DS
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
8.
9.
IN
I/O
Parameter
Tested initially and after any design or process changes that may affect these parameters.
Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I
CHZ
Parameter
, t
CLZ
, t
EOHZ
Z
0
[8]
, and t
=50
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWS
BWS
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
Chip Enable Hold After CLK Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid
(a)
EOLZ
V
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage.
[1:0]
[1:0]
L
=1.5V
Input Capacitance
I/O Capacitance
, GW,BWE Set-Up Before CLK Rise
, GW,BWE Hold After CLK Rise
OL
R
/I
OH
L
=50
and load capacitance. Shown in (a) and (b) of AC test loads.
Over the Operating Range
[10, 11]
CHZ
Description
[10, 11]
(max) is less than t
OUTPUT
Description
3.3V
INCLUDING
[10, 12]
[10, 12]
JIG AND
SCOPE
CLZ
5 pF
(min).
T
V
[9]
A
DD
= 25 C, f = 1 MHz,
(b)
R1=317
= 5.0V
Test Conditions
R2=351
GND
3.0V
3.0 ns
Min.
8.5
3.0
3.0
1.5
0.5
2.0
2.0
2.0
0.5
2.0
1.5
0.5
2.0
0.5
0.5
0.5
0
0
10%
-117
Max.
7.5
3.5
3.5
3.5
ALL INPUT PULSES
90%
Max.
5.0
8.0
Min.
4.0
4.0
1.5
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
1.5
0.5
2.0
0.5
10
0
0
-100
CY7C1338B
Max.
8.0
3.5
3.5
3.5
90%
Page 9 of 18
10%
Unit
pF
pF
3.0 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns