LH28F160S3HT-L10A Sharp Microelectronics, LH28F160S3HT-L10A Datasheet
LH28F160S3HT-L10A
Specifications of LH28F160S3HT-L10A
LHF16KA7
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LH28F160S3HT-L10A Summary of contents
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... P P RELIMINARY RODUCT LH28F160S3HT-L10A 16M (2M × 8/1M × 16) S PECIFICATIONS ® Flash Memory (Model No.: LHF16KA7) Issue Date: March 22, 2001 Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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INTRODUCTION ...................................................... 3 1.1 Product Overview ................................................ 3 2 PRINCIPLES OF OPERATION ................................ 6 2.1 Data Protection ................................................... 7 3 BUS OPERATION.................................................... 7 3.1 Read ................................................................... 7 3.2 Output Disable .................................................... 7 3.3 Standby ............................................................... 7 3.4 Deep ...
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... GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F160S3HT-L10A is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. The LH28F160S3HT-L10A is manufactured on SHARP’ ...
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... Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Product Overview The LH28F160S3HT-L10A is a high-performance 16M-bit Smart 3 Flash memory organized as 2MBx8/1MBx16. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system. The memory map is shown in Figure 3 ...
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Input Buffer Address Latch Address Counter ...
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... NC NO CONNECT: Lead is not internal connected; it may be driven or floated. LHF16KA7 Table 2. Pin Descriptions Name and Function :Inputs data during CUI write cycles in x16 mode; outputs data during memory ). Data is internally latched during a write cycle deselects the device and reduces power consumption ...
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... PRINCIPLES OF OPERATION The LH28F160S3HT-L10A Flash memory includes an on-chip WSM to manage block erase, full chip erase, (multi) word/byte write and block lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
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... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier ...
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... Block 31 be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Table 3.1. Bus Operations(BYTE#= ≤V , memory contents can be read, but not altered. PP PPLK or V PPLK and CC1 WE# Address 0- OUT High High High Z See V X Note 5 IH Figure 4 See Table V X Note WE# Address 0 OUT High High High Z See V X Note 5 ...
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... QA=Query Offset Address. BA=Address within the block being erased or locked. WA=Address of memory location to be written. 3. SRD=Data read from status register. See Table 14 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) ...
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... Future Use NOTE selects the specific block status code to be read. See Figure 4 for the device identifier code memory map. LHF16KA7 4.3 Read Status Register Command The status register may be read to determine when a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration is complete and whether the operation completed successfully(see Table 14) ...
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Query Command Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 7~11 retrieve the critical information to write, erase and otherwise control the flash component. A ...
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CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Offset Length (Word Address) 10H,11H,12H ...
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Device Geometry Definition This field provides critical details of the flash device geometry. Offset Length (Word Address) 27H 01H 28H,29H 02H 2AH,2BH 02H 2CH 01H 2DH,2EH 02H 2FH,30H 02H 4.5.5 SCS OEM Specific Extended Query Table Certain flash ...
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Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence appropriate sequencing and an ...
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... XSR.7. The Multi Word/Byte Write command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F160S3HT-L10A has two buffers error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded in multi word/byte write command. Status register bit SR.4 will be set to " ...
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... Read Status Register and (Multi) Word/Byte Write Resume. After (Multi) Word/Byte Write Resume command is written to the flash memory, the WSM will continue the (multi) word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and STS will ...
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Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V individual block lock-bits can be set using the Set Block Lock-Bit command. ...
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STS Configuration Command The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device ...
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WSMS BESS ECBLBS 7 6 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H, Block Address Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register No Suspend 0 SR.7= Word/Byte Write 1 Full Status Check if Desired Word/byte Write Complete FULL STATUS ...
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Start Write E8H, Start Address Read Extend Status Register 0 Write Buffer XSR.7= Time Out 1 Write Word or Byte Count (N)-1, Start Address Write Buffer Data, Start Address X=1 Yes Yes Abort Buffer Write ...
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FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Read Status Register 1 SR.3= V Range Error SR.1= Device Protect Error 0 1 Command Sequence SR.4,5= Error 0 1 Multi Word/Byte Write SR.4= Error 0 Multi ...
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Start Write B0H Read Status Register 0 SR. SR.6= 1 (Multi) Word/Byte Write Read Read or Write ? Read Array Data (Multi) Word/Byte Write Loop No Done? Yes Write D0H Block Erase Resumed Figure 10. Block Erase ...
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Start Write B0H Read Status Register 0 SR.7= 1 (Multi) Word/Byte Write 0 SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH (Multi) Word/Byte Write Read Array Data Resumed Figure 11. (Multi) ...
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Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Block Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error PP ...
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Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error SR.1= Device ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control accommodate multiple memory connections. Three- Line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. ...
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... V , the CUI must be placed in PPLK read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block and full chip erasure, (multi) word/byte writing or block lock-bit configuration during power transitions ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration .....-40°C to +85°C Temperature under Bias............... -40°C to +85°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Write Current CCW ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage during PPLK PP Normal Operations V ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV ...
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Standby V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/ RP#( NOTE: CE# is defined ...
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Standby V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) (DQ ...
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AC CHARACTERISTICS - WRITE OPERATIONS Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V Setup to WE# Going High SHWH ...
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V ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#(F) V High Z STS( WP#( RP#( PPH3,2 PPLK V NOTES: 1. ...
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ALTERNATIVE CE#-CONTROLLED WRITES Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP# V Setup to ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP# V Setup to CE# Going High SHEH ...
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V ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#(F) V High Z STS( WP#( RP#( PPH3,2 (V) PP PPLK V NOTES ...
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RESET OPERATIONS High Z STS( RP#( High Z STS( RP#( 2.7/3. RP#( Symbol Parameter t RP# Pulse Low ...
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BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter Word/Byte Write Time t WHQV1 (using W/B write, in word t EHQV1 mode) Word/Byte Write Time t WHQV1 (using W/B write, in byte ...
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Sym. Parameter t Word/Byte Write Time WHQV1 t (using W/B write, in word mode) EHQV1 t Word/Byte Write Time WHQV1 t (using W/B write, in byte mode) EHQV1 Word/Byte Write Time (using multi word/byte write) Block Write Time (using ...
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... Device Density 160 = 16-Mbit Architecture S = Regular Block Power Supply Type 3 = Smart 3 Technology Operating Temperature Blank = 0°C ~ +70° -40°C ~ +85°C Option Order Code 1 LH28F160S3HT-L10A LHF16KA7 - Access Speed (ns) 10:100ns (3.3V), 120ns (2.7V) 13:130ns (3.3V), 150ns (2.7V) Package T = 56-Lead TSOP R = 56-Lead TSOP(Reverse Bend 56-Lead SSOP ...
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... Protecting data in specific block Setting the lock bit of the desired block and pulling WP# low disables the writing operation on that block. By using this feature, the flash memory space can be divided into, for example, the program section (locked section) and data section (unlocked section). ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...