M29DW128F70ZA6F NUMONYX, M29DW128F70ZA6F Datasheet - Page 14

• Manufacturer Part Number: M29DW128F70ZA6F
• Description: IC FLASH 128MBIT 70NS 64TBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29DW128F70ZA6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal descriptions
2
2.1
2.2
2.3
2.4
2.5
2.6
14/94
Signal descriptions
See
connected to this device.
Address Inputs (A0-A22)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the internal state machine.
Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, V
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1)
When the device is in x16 Bus mode, this pin behaves as a Data Input/Output pin (as DQ8-
DQ14). When the device is in x8 Bus mode, this pin behaves as an address pin; DQ15A–1
Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the Data Input/Output to include this pin when
the device operates in x16 bus mode and references to the Address Inputs to include this
pin when the device operates in x8 bus mode except when stated explicitly otherwise.
Chip Enable (E)
The Chip Enable pin, E, activates the memory, allowing Bus Read and Bus Write operations
to be performed. When Chip Enable is High, V
Output Enable (G)
The Output Enable pin, G, controls the Bus Read operation of the memory.
Figure 1: Logic
diagram, and
IH
. When BYTE is Low, V
Table 1: Signal
IH
IL
, all other pins are ignored.
, these pins are not used and are high
names, for a brief overview of the signals
M29DW128F