M29DW128F70ZA6F NUMONYX, M29DW128F70ZA6F Datasheet - Page 37

• Manufacturer Part Number: M29DW128F70ZA6F
• Description: IC FLASH 128MBIT 70NS 64TBGA
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29DW128F70ZA6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 128M (16Mx8, 8Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M29DW128F
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
Write to Buffer and Program Confirm command
The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and
Program command and to program the N+1 Words/bytes loaded in the Write Buffer by this
command.
Write to Buffer and Program Abort and Reset command
The Write to Buffer and Program Abort and Reset command is used to abort Write to Buffer
and Program command.
Double Word Program command
This is used to write two adjacent Words in x16 mode, simultaneously. The addresses of the
two Words must differ only in A0.
Three bus write cycles are necessary to issue the command:
1.
2.
3.
Quadruple Word Program command
This is used to write a page of four adjacent Words, in x16 mode, simultaneously. The
addresses of the four Words must differ only in A1 and A0.
Five bus write cycles are necessary to issue the command:
1.
2.
3.
4.
5.
Double byte Program Command
This is used to write two adjacent bytes in x8 mode, simultaneously. The addresses of the
two bytes must differ only in DQ15A-1.
Three bus write cycles are necessary to issue the command:
1.
2.
3.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Word to be written.
The third bus cycle latches the Address and the Data of the second Word to be written
and starts the Program/Erase Controller.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Word to be written.
The third bus cycle latches the Address and the Data of the second Word to be written.
The fourth bus cycle latches the Address and the Data of the third Word to be written.
The fifth bus cycle latches the Address and the Data of the fourth Word to be written
and starts the Program/Erase Controller.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first byte to be written.
The third bus cycle latches the Address and the Data of the second byte to be written
and starts the Program/Erase Controller.
Command interface
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