M34D64-WMN6P STMicroelectronics, M34D64-WMN6P Datasheet - Page 15
![IC EEPROM 64KBIT 400KHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M34D64-WMN6P
Manufacturer Part Number
M34D64-WMN6P
Description
IC EEPROM 64KBIT 400KHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M34D64-WMN6TP.pdf
(27 pages)
Specifications of M34D64-WMN6P
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8588-5
M34D64-WMN6P
M34D64-WMN6P
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
M34D64-W
3.7
3.8
Byte Write
After the Device Select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected (top quarter of the memory), by Write Control
(WC) being driven high, the location is not modified. The bus master terminates the transfer
by generating a Stop condition, as shown in
(data write
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same ’row’ in the memory: that is, the most significant
memory address bits (b12-b5) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data. If Write Control (WC) is high, the contents
of the addressed top quarter of the memory location are not modified. After each byte is
transferred, the internal byte address counter (the 5 least significant address bits only) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
enabled).
Figure 7.: Write mode sequences with WC = 0
Device operation
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