M58BW016FB7T3T NUMONYX, M58BW016FB7T3T Datasheet - Page 15

• Manufacturer Part Number: M58BW016FB7T3T
• Description: IC FLASH 16MBIT 70NS 80PQFP
• Manufacturer: NUMONYX

Specifications of M58BW016FB7T3T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (512K x 32)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-MQFP, 80-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: M58BW016FB7T3TCT

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
2.5
2.6
2.7
2.8
Output Disable (GD)
The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at
V
outputs are high impedance independently of Output Enable. The Output Disable pin must
be connected to an external pull-up resistor as there is no internal pull-up resistor to drive
the pin.
Write Enable (W)
The Write Enable, W, input controls writing to the command interface, Address inputs and
Data latches. Both addresses and data can be latched on the rising edge of Write Enable
(also see Latch Enable, L).
Reset/Power-down (RP)
The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware
reset is achieved by holding Reset/Power-down Low, V
inhibited to protect data, the command interface and the program/erase controller are reset.
The status register information is cleared and power consumption is reduced to deep power-
down level. The device acts as deselected, that is the data outputs are high impedance.
After Reset/Power-down goes High, V
after a delay of t
If Reset/Power-down goes Low, V
aborted, in a time of t
During power-up power should be applied simultaneously to V
at V
and Write Enable, W, should be held at V
In an application, it is recommended to associate reset/power-down pin, RP, with the reset
signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is
performing an erase or program operation, the memory may output the status register
information instead of being initialized to the default asynchronous random read.
See
power-down and power-up AC waveforms - control pins
Latch Enable (L)
The bus interface can be configured to latch the address inputs on the rising edge of Latch
Enable, L, for asynchronous latch enable controlled read or write or synchronous burst read
operations. In synchronous burst read operations the address is latched on the active edge
of the Clock when Latch Enable is Low, V
without affecting the address used by the memory. When Latch Enable is Low, V
is transparent. Latch Enable, L, can remain at V
operations.
IH
, the outputs are driven by the Output Enable. When Output Disable, GD, is at V
IL
Table 22: Reset, power-down and power-up AC characteristics
. When the supplies are stable RP is taken to V
PHEL
PLRH
or bus write operations after t
maximum, and data is altered and may be corrupted.
IL
, during a Block Erase, or a Program the operation is
IH
, the memory will be ready for bus read operations
IH
IL
. Once latched, the addresses may change
during power-up.
IL
for asynchronous random read and write
PHWL
IH
. Output Enable, G, Chip Enable, E,
IL
.
low, for more details.
, for at least t
DD
and V
and
PLPH
Signal descriptions
DDQ(IN)
Figure 17: Reset,
. Writing is
with RP held
IL
, the latch
IL
, the
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