M58BW016FB7T3T NUMONYX, M58BW016FB7T3T Datasheet - Page 21

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M58BW016FB7T3T

Manufacturer Part Number
M58BW016FB7T3T
Description
IC FLASH 16MBIT 70NS 80PQFP
Manufacturer
NUMONYX
Datasheet

Specifications of M58BW016FB7T3T

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
16M (512K x 32)
Speed
70ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Package / Case
80-MQFP, 80-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
M58BW016FB7T3TCT
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
3.2
3.2.1
Caution:
Table 5.
1. BCR = Burst configuration register.
Synchronous bus operations
For synchronous bus operations refer to
Synchronous burst read
Synchronous burst read operations are used to read from the memory at specific times
synchronized to an external reference clock.
In the M58BW016FT and M58BW016FB only, once the memory is configured in burst
mode, it is mandatory to have an active clock signal since the switching of the output buffer
data bus is synchronized to the active edge of the clock. In the absence of clock, no data is
output.
The M58BW016DT and M58BW016DB are not concerned by the paragraph above.
The burst type, length and latency can be configured. The different configurations for
synchronous burst read operations are described in
register. Refer to
In continuous burst read, one burst read operation can access the entire memory
sequentially by keeping the Burst Address Advance B at V
clock cycles. At the end of the memory address space the burst read restarts from the
beginning at address 000000h.
A valid synchronous burst read operation begins when the Burst Clock is active and Chip
Enable and Latch Enable are Low, V
the internal burst address counter on the valid Burst Clock K edge (rising or falling
depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first.
After an initial memory latency time, the memory outputs data each clock cycle (or two clock
cycles depending on the value of M9). The Burst Address Advance B input controls the
memory burst output. The second burst output is on the next clock valid edge after the Burst
Address Advance B has been pulled Low.
Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the burst
controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low
on the active clock edge, no new data is available and the memory does not increment the
internal address counter at the active clock edge even if Burst Address Advance, B, is Low.
Burst configuration
Manufacturer
register
Device
Code
Asynchronous read electronic signature operation
Figure 4
M58BW016DT
M58BW016DB
M58BW016FT
M58BW016FB
Device
All
and
Figure 5
V
V
V
V
IL
E
IL
IL
IL
IL
. The burst start address is latched and loaded into
for examples of synchronous burst operations.
Table 6
V
V
V
V
G
IL
IL
IL
IL
together with the following text.
Section 3.3: Burst configuration
GD
V
V
V
V
IH
IH
IH
IH
IL
for the appropriate number of
V
V
V
V
W
IH
IH
IH
IH
A18-A0
00000h
00001h
00001h
00005h
Bus operations
DQ31-DQ0
00000020h
00008836h
00008835h
BCR
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