TE28F640J3C115SL7HA Intel, TE28F640J3C115SL7HA Datasheet - Page 32

• Manufacturer Part Number: TE28F640J3C115SL7HA
• Description: IC FLASH 64MBIT 115NS 56TSOP
• Manufacturer: Intel

Specifications of TE28F640J3C115SL7HA

• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 860794

256-Mbit J3 (x8/x16)
9.0
9.1
32
Read Array
Output Disable
Standby
Reset/Power-Down
Mode
Read Identifier Codes
Read Query
Read Status (WSM off)
Read Status (WSM on)
Write
NOTES:
10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when V
1. See
2. OE# and WE# should never be enabled simultaneously.
3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high.
4. Refer to DC Characteristics. When V
5. X can be V
6. In default mode, STS is V
7. High Z will be V
8. See
9. See
V
is V
reset/power-down mode.
is within specification.
Table 12. Bus Operations
PENH
OH
Table 13 on page 33
Section 10.2, “Read Identifier Codes” on page 39
Section 10.3, “Read Query/CFI” on page 41
Mode
voltages.
when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or
IL
or V
Bus Operations
This section provides an overview of device bus operations. The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of all in-
system read, write, and erase operations of the device via the system bus.
Device commands are written to the CUI to control all of the flash memory device’s operations.
The CUI does not occupy an addressable memory location; it’s the mechanism through which the
flash device is controlled.
Bus Operations Overview
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus cycles.
OH
IH
with an external pull-up resistor.
for control and address signals, and V
RP#
V
V
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IH
IH
IL
OL
for valid CE configurations.
when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It
CE[2:0]
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
X
PEN
(1)
≤ V
OE#
PENLK
V
V
V
V
V
V
V
X
X
IH
IH
IL
IL
IL
IL
IL
(2)
for read query data.
, memory contents can be read, but not altered.
WE#
for read identifier code data.
V
V
V
V
V
V
V
X
X
IH
IH
IH
IH
IH
IH
IL
PENLK
(2)
Address
Table 17
or V
Table
10.3
See
See
X
X
X
X
X
X
X
PENH
for V
V
VPEN
PENH
X
X
X
X
X
X
X
X
PEN
. See DC Characteristics for V
D[15:8] = High Z
D[6:0] = High Z
D7 = D
Data
High Z
High Z
High Z
Note 8
Note 9
D
D
D
OUT
OUT
IN
(3)
OUT
PEN
High Z
High Z
High Z
High Z
(default
mode)
= V
STS
X
X
X
PENH
(7)
(7)
(7)
(7)
Datasheet
PENLK
and V
6,10,11
Notes
4,5,6
and
CC