MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 26

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

MultiBurst operation is controlled by 5 bits in the MultiBurst Mode Control register: BURST_EN,
CLK_INV, LATENCY, HOLD and LENGTH. For full details on this register, please refer to
Section 7.
MultiBurst mode read cycles are supported via the CLK input, which is enabled by setting the
BURST_EN bit in the MultiBurst Mode Control register.
To determine whether the rising or falling edge of the CLK input is sampled (called CLK0), the
CLK_INV bit in the MultiBurst Mode Control register must be specified. When the CLK_INV bit
is set to 0, CE# and OE# are sampled on the rising edge of CLK; when the CLK_INV bit is set to 1,
sampling is done on the falling edge of CLK.
Notes: 1. When the CLK_INV bit is set to 1, sampling is done on the falling edge of CLK, and an
The LATENCY field is the third field that must be set in the MultiBurst Mode Control register.
When the LATENCY field is set to 0, the host can latch the first 16-bit data word two clock cycles
after CLK0. This time can be extended by up to seven clock cycles by programming the LATENCY
field. After latching the first word, additional 16-bit data words can be latched on each subsequent
clock cycle.
The HOLD bit in the MultiBurst Mode Control register can be set to hold each data word valid for
two clock cycles rather than one.
The LENGTH field in the MultiBurst Mode Control register must be programmed with the length
of the burst to be performed. As read cycles from the flash are volatile, each burst cycle must read
exactly this number of words.
The CLK input can be toggled continuously or can be halted. When halting the CLK input, the
following guidelines must be observed:
Two modes are provided to improve compatibility with hosts which can provide only a high CLK
frequency. In each of these modes, a clock divider is used to generate only one DiskOnChip clock
cycle for every two cycles of the CLK input.
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• After asserting OE# and CE#, LATENCY + 2 CLK cycles are required prior to latching the
• If the HOLD bit is set to 0, the host must provide one rising CLK edge for each word read,
• If the HOLD bit is set to 1, the host must provide two rising CLK edges for each word read,
• Subsequent toggling of the CLK is optional.
• Hold mode: Causes each data word to be held for two clock cycles instead of one. Best used
2. Burst mode is disabled upon assertion of the RSTIN# input, and the signal may therefore
first word (2.5 CLK cycles if CLK_INV is set to 1).
except for the last word latched, for which CLK does not need to be toggled.
except for the last word, for which the second of the two CLK rising edges is not required.
on platforms which support Hold mode and offer large burst lengths.
additional half-clock cycle of latency is incurred. Data continues to be output on D[15:0]
on the rising edge of CLK.
be left floating.
Data Sheet (Preliminary) Rev. 0.3
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
92-DS-1105-00