MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 28

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

4.2
DiskOnChip G4 provides a DMARQ# output that enables up to 256KB to be read from the flash by
the host DMA controller. During DMA operation, the DMARQ# output is used to notify the host
DMA controller that the next flash page is ready to be read, and the IRQ# pin indicates whether an
error occurred while reading the data from the flash or the end of the DMA transfer was reached.
The DMARQ# output sensitivity is chosen by setting the EDGE bit in the DMA Control register[0]:
The following steps are required to initiate a DMA operation:
1. Initialize the platform’s DMA controller to transfer 512 bytes upon each assertion of the
2. Set the bits in the Interrupt Control register (see Section 7) to enable interrupts on an ECC error
3. Write to the DMA Control register[0] to set the DMA_EN bit, the EDGE bit and the number of
4. The host DMA controller reads one sector (512 bytes) of data from DiskOnChip G4.
5. If an ECC error is detected, an interrupt is generated (IRQ# signal asserted), the transfer of data
6. The process continues until the last sector is read, after which DiskOnChip G4 generates an
Notes: 1. DiskOnChip G4 generates a DMA request (DMARQ# signal asserted) after the last byte
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• Edge − The DMARQ# output pulses to logic 0 for 250~500 nsec to indicate to the DMA
• Level − The DMARQ# output is asserted to initiate the block transfer and returns to the
DMARQ# output. If the DMA controller supports an edge-sensitive DMARQ# signal, then
initialize the DMA controller to transfer 512 bytes upon each DMA request. If the DMA
controller supports a level-sensitive DMARQ# signal, then initialize the DMA controller to
transfer data while DMARQ# is asserted.
and at the end of the DMA operation.
sectors (SECTOR_COUNT field) to be transferred to the host. At this point, DiskOnChip G4
generates a DMA request to indicate to the host that it is ready to transfer data.
is halted and control is returned to the host. If no ECC error is detected, a DMA request is
initiated (DMARQ# signal asserted) and the next sector is read by the host.
interrupt (IRQ# signal asserted) to indicate that it has transferred the last byte.
DMA Operation
controller that a flash page is ready to be read. The EDGE bit is set to 1 for this mode.
negated state at the end of each block transfer. The EDGE bit is set to 0 for this mode.
2. DMA operation may be aborted after transferring each 512-byte block (step 4) by
is read. It may therefore be necessary to clear the final DMA request from the DMA
controller.
clearing the DMA_EN bit in the DMA Control register[0].
Data Sheet (Preliminary) Rev. 0.3
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
92-DS-1105-00