MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 51

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

8.
8.1
DiskOnChip G4 can function both as a flash disk and as the system boot device..
If DiskOnChip G4 is configured as a flash disk and as the system boot device, it contains the boot
loader, an OS image and a file system. In such a configuration, DiskOnChip G4 can serve as the
only non-volatile device on board.
8.2
In legacy architecture the boot code is executed from a boot ROM, and the drivers are usually
loaded from the storage device.
When using DiskOnChip G4 as the system boot device, the CPU fetches the first instructions from
the DiskOnChip G4 Programmable Boot Block, which contains the IPL. Since in most cases this
block cannot hold the entire boot loader, the IPL runs minimum initialization, after which the
Secondary Program Loader (SPL) is copied to RAM from flash. The remainder of the boot loader
code then runs from RAM.
The SPL is located in a separate (binary) partition on DiskOnChip G4, and can be hardware
protected if required.
8.2.1
Platforms that host CPUs that wake up in MultiBurst mode should use Asynchronous Boot mode
when using DiskOnChip G4 as the system boot device.
During platform initialization, certain CPUs wake up in 32-bit mode and issue instruction fetch
cycles continuously. An Intel XScale CPU, for example, initiates a 16-bit read cycle, but after the
first word is read, it continues to hold CE# and OE# asserted while it increments the address and
reads additional data as a burst.
Once in Asynchronous Boot mode, the CPU can fetch its instruction cycles from the DiskOnChip
G4 Programmable Boot Block. After reading from this block and completing boot, DiskOnChip G4
returns to derive its internal clock signal from the CE#, OE#, and WE# inputs. Please refer to
Section 10.3 for read timing specifications for Asynchronous Boot mode.
8.2.2 Virtual RAM Boot
The Virtual RAM Boot feature utilizes the 2KB physical IPL SRAM to provide XIP access to up to
8KB of flash data, without requiring any prior knowledge of the device architecture. This feature
can be used to support the Processor Secure Boot requirements. The Virtual RAM Boot feature is
intended for platforms that support the DiskOnChip G4 BUSY# output.
When DiskOnChip G4 is configured with the Virtual RAM Boot feature active, DiskOnChip
remains in virtual RAM whenever it is in Reset mode. While in this mode, read cycles from the
entire DiskOnChip 8KB memory window return virtual RAM data. Access to an address that is not
the physical 2KB SRAM initiates a download operation in which the required data is copied from
the NAND flash to the physical SRAM. The DiskOnChip BUSY# output is asserted (low) for the
51
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Introduction
Boot Replacement
Asynchronous Boot Mode
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Data Sheet (Preliminary) Rev. 0.3
C
HIP
G4
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
92-DS-1105-00