MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 52

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MD8331-D2G-V3-X-P

Manufacturer Part Number
MD8331-D2G-V3-X-P
Description
IC MDOC G4 2GB 69-FBGA
Manufacturer
SanDisk
Datasheet

Specifications of MD8331-D2G-V3-X-P

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
2G (256M x 8)
Speed
33ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
69-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
585-1149-2
MD8831-D2G-V3-X-P
MD8832-D2G-V3-X-P

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MD8331-D2G-V3-X-P
Manufacturer:
INTEL
Quantity:
480
Part Number:
MD8331-D2G-V3-X-P
Manufacturer:
M-SYSTEM
Quantity:
586
Part Number:
MD8331-D2G-V3-X-P
Manufacturer:
SanDisk
Quantity:
10 000
Part Number:
MD8331-D2G-V3-X-P/Y
Manufacturer:
SanDisk
Quantity:
10 000
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
duration of the download, to indicate that the data is not ready, holding the platform in a wait state.
When the download is completed the /BUSY line will be negated (high). This handshake
mechanism is compatible with CPU bus controllers that support automatic insertion of wait states
based on the state of a /RDY signal. The platform must be capable of being held in a wait state for
an arbitrary period during each download process, without interference from watchdog timers.
The download is transparent to software, and XIP and random access from any location within the
8KB virtual address space are therefore supported.
For more information on how to boot from DiskOnChip G4 in Virtual RAM Boot mode, please
contact your local M-Systems sales office
8.2.3
Paged RAM Boot
The Paged RAM Boot feature separates the 2KB IPL SRAM into two 1KB sections. The first
section provides constant data, while the other section can be downloaded with flash data. One
application of this feature is to support the processors Secure Boot requirements. The Paged RAM
Boot feature does not support XIP (unlike the Virtual RAM Boot feature), but also does not require
support of the BUSY# output.
After a hardware or software reset, DiskOnChip G4 initializes the first 2KB of RAM from data
stored in a fixed location on DiskOnChip G4. The Paged RAM Boot feature permits 1KB of the
internal SRAM to be downloaded upon receiving a command sequence from one of many 1KB
virtual pages (up to 124 sections of 2KB). Since the DiskOnChip G4 BUSY# output is not asserted
by a page-load operation, a polling procedure is required to determine when the download is
complete. A XIP operation from the DiskOnChip G4 RAM is not supported during this polling
operation, so it must be executed instead from system RAM or ROM.
Normally, the data in the first 1KB of RAM is fixed, while the second 1 KB is downloaded upon
command.
To support platforms that boot from the top rather than the bottom of memory, DiskOnChip G4 can
be configured with an alternate memory map where the top 1KB of the DiskOnChip G4 address
space returns fixed RAM data, while the 1KB below that is downloadable.
When multiple DiskOnChip G4 devices are cascaded, Paged RAM downloads occur only on the
first DiskOnChip in the cascaded configuration (device-0). The other cascaded devices move to
Reset mode when a Paged RAM download is initiated.
For more information on booting from DiskOnChip G4 in Paged RAM Boot mode, please contact
your local M-Systems sales office.
52
Data Sheet (Preliminary) Rev. 0.3
92-DS-1105-00

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