MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 58

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

9.5
9.5.1 Hardware Configuration
To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to
the host interrupt input.
Note: A nominal 10 KΩ pull-up resistor must be connected to this pin/ball.
9.5.2
Configuring the software to support the IRQ# interrupt is performed in two stages.
Stage 1
Configure the software so that when the system is initialized, the following steps occur:
1. The correct value is written to the Interrupt Control register to configure DiskOnChip G4 for:
2. The host interrupt is configured to the selected input sensitivity, either edge or level-triggered.
3. The handshake mechanism between the interrupt handler and the OS is initialized.
4. The interrupt service routine to the host interrupt is connected and enabled.
Stage 2
Configure the software so that for every long flash I/O operation, the following steps occur:
1. The correct value is written to the Interrupt Control register to enable the IRQ# interrupt.
2. The flash I/O operation starts.
3. Control is returned to the OS to continue other tasks. When the IRQ# interrupt is received,
4. The OS either returns control immediately to the TrueFFS driver, or waits for the appropriate
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Note: Refer to Section 7 for further information on the value to write to this register.
Note: Refer to Section 7 for further information on the value to write to this register.
other interrupts are disabled and the OS is flagged.
condition to return control to the TrueFFS driver.
• Interrupt source: Flash ready, data protection, last byte during DMA has been transferred, or
• Output sensitivity: Either edge or level-triggered
Implementing the Interrupt Mechanism
Software Configuration
BCH ECC error has been detected (used during multi-page DMA operations).
Data Sheet (Preliminary) Rev. 0.3
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
92-DS-1105-00