MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 62

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

8-Bit (Byte) Data Access Mode
When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines
D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even
address accesses to the appropriate byte lane of the flash and RAM.
Host address SA0 must be connected to DiskOnChip G4 A0, SA1 must be connected to A1, etc.
16-Bit (Word) Data Access Mode
To set DiskOnChip G4 to work in 16-bit mode, the IF_CFG pin/ball must be connected to VCC.
In 16-bit mode, the Programmable Boot Block is accessed as a true 16-bit device. It responds with
the appropriate data when the CPU issues either an 8-bit or 16-bit read cycle. The flash area is
accessed as a 16/32-bit device, regardless of the interface bus width. This has no affect on the
design of the interface between DiskOnChip G4 and the host. The TrueFFS driver handles all issues
regarding moving data in and out of DiskOnChip G4.
See Table 4 for A0 and IF_CFG settings for various functionalities with 8/16-bit data access.
32-Bit (Double Word) Data Access Mode
In a 32-bit bus system that cannot execute byte- or word-aligned accesses, the system address lines
SA0 and SA1 are always 0. Consecutive double words (32-bit words) are differentiated by SA2
toggling. Therefore, in 32-bit systems that support only 32-bit data access cycles, DiskOnChip G4
signal A0 is connected to VSS and A1 is connected to the first system address bit that toggles; i.e.,
SA2.
62
SA13
A12
Note:
SA12
A11
The prefix “S” indicates system host address lines
A0
0
0
1
1
SA11
A10
Figure 17: Address Shift Configuration for 32-Bit Data Access Mode
Table 4: Active Data Bus Lines in 8/16-Bit Configuration
SA10
A9
IF_CFG
1
0
0
1
SA9
A8
Data Sheet (Preliminary) Rev. 0.3
16-bit access through both buses
8-bit access to even bytes through low 8-bit bus
8-bit access to odd bytes through low 8-bit bus
Illegal
SA8
A7
DiskOnChip G4
System
SA7
Host
A6
SA6
A5
Functionality
SA5
A4
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
SA4
A3
SA3
A2
SA2
A1
SA1
A0
92-DS-1105-00
SA0