MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 77

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Applicable only if HOLD=0, FIFO=1, INV=1 in the Burst Mode Control Register.
11. Applicable only if HOLD=1, FIFO=0, INV=1 in the Burst Mode Control Register.
12. Applicable only with the SRAM interface. For the Muxed interface, Tsu(AVD), Tho(AVD), Tw(AVD) and Tho(AVD-OE) apply as shown in
77
CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be referenced
instead to the time of CE# asserted.
CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time of CE# negated.
No load (CL = 0 pF).
Applicable only if CLK_INV bit of the Burst Mode Control Register 0.
Applicable only if CLK_INV bit of the Burst Mode Control Register is 1.
Applicable only if HOLD=0, FIFO=0, INV=0 in the Burst Mode Control Register.
Applicable only if HOLD=0, FIFO=1, INV=0 in the Burst Mode Control Register.
Applicable only if HOLD=1, FIFO=0, INV=0 in the Burst Mode Control Register.
Applicable only if HOLD=0, FIFO=0, INV=1 in the Burst Mode Control Register.
Table 12 and Figure 22.
T
REC
T
T
Symbol
T
W
T
T(CLK)
REC
Tho(A)
Tsu(A)
(OE-CLK1)
LOZ
HIZ
(CLK0)
(OE)
(D)
(D)
CLK high pulse width
CLK low pulse width
CLK low pulse width
CLK low pulse width
CLK low pulse width
CLK low pulse width
CLK low pulse width
CLK period
CLK period
CLK period
CLK period
CLK period
CLK period
OE# negated to start of next
cycle
OE#
OE#
Address to OE#
OE#
OE#
edge which samples OE_ low
(trec(OE) + tsu(OE0-CLK1)
OE#
edge after falling edge which
samples OE_ low (trec(OE) +
tsu(OE0-CLK0) + tw(CLK0))
2
to D driven
to D Hi-Z delay
setup to next CLK rising
setup to next CLK rising
Data Sheet (Preliminary) Rev. 0.3
to Address hold time
Description
6
7
8
9
10
11
1, 3
6
7
8
9
10
11
setup time
11
2
4,5
4,5
1,12
1,12
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
VCC=1.65-1.95V
Min
19
19
12
12
55
32
32
50
32
31
17
31
24
28
-8
VCCQ=VCC
8
8
8
Max
20
3
Units
Ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
92-DS-1105-00