MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet - Page 28

• Manufacturer Part Number: MD5811-D256-V3Q18-P
• Description: IC MDOC P3 256MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD5811-D256-V3Q18-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 256M (32M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6
Upon power-up or when the RSTIN# signal is asserted, the DE automatically downloads the Initial
Program Loader (IPL) to the Programmable Boot Block. The IPL is responsible for starting the
booting process. The download process is quick, and is designed so that when the CPU accesses
Mobile DiskOnChip P3 for code execution, the IPL code is already located in the Programmable
Boot Block.
In addition, the DE downloads the data protection rules from the flash to the Protection State
Machines (PSM), so that Mobile DiskOnChip P3 is secure and protected from the first moment it is
active.
During the download process, Mobile DiskOnChip P3 asserts the BUSY# signal to indicate to the
system that it is not yet ready to be accessed. Once BUSY# is negated, the system can access
Mobile DiskOnChip P3.
A failsafe mechanism prevents improper initialization due to a faulty VCC or invalid assertion of
the RSTIN# input. Another failsafe mechanism is designed to overcome possible NAND flash data
errors. It prevents internal registers from powering up in a state that bypasses the intended data
protection. In addition, any attempt to sabotage the data structures causes the entire DiskOnChip to
become both read and write protected, and completely inaccessible.
3.7
M-Systems’ x2 technology implements 4-bit Error Detection Code/Error Correction Code
(EDC/ECC), based on a patented combination of Bose, Chaudhuri and Hocquenghem (BCH) and
Hamming code algorithms. Error Detection Code (EDC) is implemented in hardware to optimize
performance, while Error Correction Code (ECC) is performed in software, when required, to save
silicon costs.
Each time a 256-byte page is written, additional parity bits are calculated and written to the flash.
Each time data is read from the flash, the parity bits are read and used to calculate error locations.
The Hamming code can detect 2 errors per page and correct 1 error per page. The BCH code can
detect and correct 4 errors per page. It can detect 5 errors per page with a probability of 99.9%. It
ensures that the minimal amount of code required is used for detection and correction to deliver the
required reliability without degrading performance.
3.8
Mobile DiskOnChip P3 uses a two-stage pipeline mechanism, designed for maximum performance
while enabling on-the-fly data manipulation, such as read/write protection and Error
Detection/Error Correction. Refer to technical note TN-DOC-014, Pipeline Mechanism in
DiskOnChip, for further information.
3.9
The Control and Status block contains registers responsible for transferring address, data and
control information between the DiskOnChip TrueFFS driver and the flash media. Additional
registers are used to monitor the status of the flash media (ready/busy) and the DiskOnChip
controller. For further information on the DiskOnChip registers, refer to Section 8.
25
Download Engine (DE)
Error Detection Code/Error Correction Code (EDC/ECC)
Data Pipeline
Control and Status
Data Sheet, Rev. 0.3
Mobile DiskOnChip P3
93-SR-009-8L