MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet - Page 32

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MD5811-D256-V3Q18-P

Manufacturer Part Number
MD5811-D256-V3Q18-P
Description
IC MDOC P3 256MB 48-TSOP
Manufacturer
SanDisk
Datasheet

Specifications of MD5811-D256-V3Q18-P

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
256M (32M x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Note: Mobile DiskOnChip P3 does not support MultiBurst write operations.
MultiBurst operation is controlled by 5 bits in the MultiBurst Mode Control register: BURST_EN,
CLK_INV, LATENCY, HOLD and LENGTH. For full details on this register, please refer to
Section 8.
MultiBurst mode read cycles are supported via the CLK input, which is enabled by setting the
BURST_EN bit in the MultiBurst Mode Control register.
To determine whether the rising or falling edge of the CLK input is sampled (called CLK0), the
CLK_INV bit in the MultiBurst Mode Control register must be specified. When the CLK_INV bit
is set to 0, CE# and OE# are sampled on the rising edge of CLK; when the CLK_INV bit is set to 1,
sampling is done on the falling edge of CLK.
Notes: 1. When the CLK_INV bit is set to 1, sampling is done on the falling edge of CLK, and an
29
2. The CLK input is disabled upon the assertion of the RSTIN# input and may therefore be
Internal data transfers
External data transfers
additional half-clock cycle of latency is incurred. Data continues to be output on D[15:0]
on the rising edge of CLK.
left floating.
Flash Planes to FIFO
Data transfer from
Data transfer from
/DiskOnChip_OE
FIFO to Host
/Flash_OE
16-bit to
Host
FIFO
Figure 11: MultiBurst Operation
16-bit Transfer
Data Sheet, Rev. 0.3
32-bit Transfer
16-bit Transfer
16-bit Data
16-bit Data
16-bit Transfer
32-bit Transfer
W
W
O
R
D
O
R
D
0
1
Flash Plane
Flash Plane
16-bit Transfer
Mobile DiskOnChip P3
93-SR-009-8L

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