MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet - Page 39

• Manufacturer Part Number: MD5811-D256-V3Q18-P
• Description: IC MDOC P3 256MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD5811-D256-V3Q18-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 256M (32M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1
This is the mode in which standard operations involving the flash memory are performed. Normal
mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control
Confirmation register. The boot detector circuit triggers the software to set the device to Normal
mode.
A write cycle occurs when both the CE# and WE# inputs are asserted. Similarly, a read cycle occurs
when both the CE# and OE# inputs are asserted. Because the flash controller generates its internal
clock from these CPU cycles and some read operations return volatile data, it is essential that the
timing requirements specified in Section 11.3 be met. It is also essential that read and write cycles
not be interrupted by glitches or ringing on the CE#, WE#, and OE# address inputs. All inputs to
Mobile DiskOnChip P3 are Schmidt Trigger types to improve noise immunity.
6.2
In Reset mode, Mobile DiskOnChip P3 ignores all write cycles, except for those to the DiskOnChip
Control register and Control Confirmation register. All register read cycles return a value of 00H.
Before attempting to perform a register read operation, the device is set to Normal mode by
TrueFFS software.
6.3
While in Deep Power-Down mode, Mobile DiskOnChip P3’s quiescent power dissipation is
reduced by disabling internal high current consumers (e.g. voltage regulators, input buffers,
oscillator etc.). The following signals are also disabled in this mode:
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To enter Deep Power-Down mode, a proper sequence must be written to the Mobile DiskOnChip
P3 Control registers and the CE# input must be negated. All other inputs should be VSS or VCC.
When in Normal mode, asserting the RSTIN# signal and holding it in low state puts the device in
Deep Power-Down mode. When the RSTIN# signal is released, the device is set in Reset mode.
In Deep Power-Down mode, write cycles have no effect and read cycles return indeterminate data
(Mobile DiskOnChip P3 does not drive the data bus). Entering Deep Power-Down mode and then
returning to the previous mode does not affect the value of any register.
To exit Deep Power-Down mode, use one of the following methods:
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Standard interface: Input buffers A[12:0], WE#, D[15:0] and OE# (when CE# is negated)
Multiplexed interface: Input buffers AD[15:0], AVD#, WE# and OE# (when CE# is negated).
Read four times from address 1FFFH (Programmable Boot Block). The data returned is
undefined.
Perform a single read cycle from the Programmable Boot Block with an extended access time
and address hold time as specified in the timing diagrams. The data returned will be correct.
Please note that this option can only be used with a standard interface, not with a multiplexed
interface.
Toggle the DPD input as defined by the DPD Control register.
Normal Mode
Reset Mode
Deep Power-Down Mode
Data Sheet, Rev. 0.3
Mobile DiskOnChip P3
93-SR-009-8L