MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet - Page 80

• Manufacturer Part Number: MD5811-D256-V3Q18-P
• Description: IC MDOC P3 256MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD5811-D256-V3Q18-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 256M (32M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.6 Power Supply Sequence
When operating Mobile DiskOnChip P3 with separate power supplies powering the VCCQ and
VCC rails, it is desirable to turn both supplies on and off simultaneously. Providing power to one
supply rail and not the other (either at power-on or power-off) can cause excessive power
dissipation. Damage to the device may result if this condition persists for more than 500 msec.
11.3.7 Power-up Timing
Mobile DiskOnChip P3 is reset by assertion of the RSTIN# input. When this signal is negated,
Mobile DiskOnChip P3 initiates a download procedure from the flash memory into the internal
Programmable Boot Block. During this procedure, Mobile DiskOnChip P3 does not respond to read
or write accesses.
Host systems must therefore observe the requirements described below for first access to Mobile
DiskOnChip P3. Any of the following methods may be employed to guarantee first-access timing
requirements:
•
•
•
•
Hosts that use Mobile DiskOnChip P3 to boot the system must employ option 4 above or use
another method to guarantee the required timing of the first-time access.
77
1.
2.
3.
4.
5.
6.
7.
Use a software loop to wait at least Tp (BUSY1) before accessing the device after the reset
signal is negated.
Poll the state of the BUSY# output.
Poll the DL_RUN bit of the Download Status register until it returns 0. The DL_RUN bit will
be 0 when BUSY# is negated.
Use the BUSY# output to hold the host CPU in wait state before completing the first access
which will be a RAM read cycle. The data will be valid when BUSY# is negated.
Symbol
t
HIZ
CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be
referenced instead to the time of CE# asserted.
CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time of CE# negated.
No load (CL = 0 pF).
Applicable only if the CLK_INV bit of the MultiBurst Mode Control register is 0.
Applicable only if the CLK_INV bit of the MultiBurst Mode Control register is 1.
Applicable only if the HOLD bit of the MultiBurst Mode Control register is 0.
Applicable only if the HOLD bit of the MultiBurst Mode Control register is 1
(D)
OE#
driven
OE#
1,3
to D
to D Hi-Z delay
Description
Normal operation
1
Data Sheet, Rev. 0.3
VCC=2.5-3.6V
VCCQ=VCC
Min
TBD
Max
5
VCCQ=1.65-2.0V
VCC=2.5-3.6V
Min
Mobile DiskOnChip P3
TBD
Max
5
93-SR-009-8L
Units
ns
ns