MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet

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MD2433-D8G-V3Q18-X-P

Manufacturer Part Number
MD2433-D8G-V3Q18-X-P
Description
IC MDOC H1 8GB 115-FBGA
Manufacturer
SanDisk
Datasheet

Specifications of MD2433-D8G-V3Q18-X-P

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Speed
64ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-30°C ~ 85°C
Package / Case
115-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
MD2433-D8G-V3Q18-X-P
Manufacturer:
SANDISK
Quantity:
18 120
Part Number:
MD2433-D8G-V3Q18-X-P
Manufacturer:
M-SYSTEM
Quantity:
363
Part Number:
MD2433-D8G-V3Q18-X-P
Manufacturer:
SanDisk
Quantity:
10 000
Highlights
mDOC H1 is one of the industry’s most
efficient memory solutions for high capacity
data and code storage, using 90 nm process
NAND flash and x2 technology from
msystems.
x2 technology enables NAND flash to achieve
highly reliable, high-performance data and code
storage with a specially designed error detection
and correction mechanism, optimized file
management, and proprietary algorithms for
enhanced performance.
This technology provides a robust, high-
capacity memory solution to answer the needs
of new multimedia devices such as PDA, smart
phones, music phones, game phones and
camera phones.
Further cost benefits derive from the cost
effective architecture of mDOC H1, which
includes a boot block that can replace expensive
NOR flash, and incorporates both the flash
memory and an embedded controller in a single
package.
mDOC H1 provides:
1
Flash disk for both code and data storage
Low voltage: 1.8V or 3.3 I/O (auto-detect),
3.3V core
Hardware protection and security-enabling
features
High capacity: 4Gb (512MB) and 8Gb
(1GB)
Device cascade capacity up to two devices:
16Gb (2GB)
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
High Capacity Flash Disk with NAND and x2 Technology
Data Sheet, Rev. 1.1
Performance
Protection & Security-Enabling Features
Reliability and Data Integrity
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface.
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC) tailored for NAND flash
technology
Maximized flash endurance with TrueFFS
Support for major mobile operating systems
(OSs), including: Symbian, Windows
Mobile, Palm, Nucleus, Linux
Compatible with major CPUs, including
TI OMAP, Intel XScale, FreeScale MX, and
Qualcomm MSMxxxx
Access time: 64 nsec
Sustained read: 8 MB/sec
Sustained write: 3.8 MB/sec
16-byte Unique Identification (UID)
number
6KByte user-controlled One Time
Programmable (OTP) area
A configurable hardware-protected partition
for data and code:
Hardware- and software-driven, on-the-fly
EDC and ECC algorithms
Read-only mode
Write-only mode
Protection key and LOCK# signal
Sticky Lock (SLOCK) to lock boot
partition
Protected Bad Block Table
Data Sheet, Rev. 1.1
95-DT-1104-01
®

Related parts for MD2433-D8G-V3Q18-X-P

MD2433-D8G-V3Q18-X-P Summary of contents

Page 1

... Further cost benefits derive from the cost effective architecture of mDOC H1, which includes a boot block that can replace expensive NOR flash, and incorporates both the flash memory and an embedded controller in a single package. mDOC H1 provides: Flash disk for both code and data storage Low voltage: 1 ...

Page 2

Error Detection Code/Error Correction Code (EDC/ECC), based on a patented combination of BCH and Hamming code algorithms, tailored for NAND flash technology Guaranteed data integrity after power failure Transparent bad-block management Dynamic and static wear-leveling Boot Capability Programmable Boot ...

Page 3

R H EVISION ISTORY Revision Date 0.1 December 2004 0.2 March 2005 0.3 June 2005 0.4 June 2005 0.5 July 2005 0.6 August 2005 1.0 December 2005 1.1 August 2006 3 Description Updated system interface description Updated device cascading information ...

Page 4

T C ABLE OF ONTENTS 1. Product Overview ...................................................................................................................... 8 1.1 Product Description ............................................................................................................ 8 1.2 Standard Interface .............................................................................................................. 9 1.2.1 Ball Diagram ......................................................................................................................... 9 1.2.2 System Interface ................................................................................................................ 11 1.2.3 Signal Description .............................................................................................................. 12 1.3 Multiplexed Interface ........................................................................................................ 14 ...

Page 5

... Wear-Leveling .................................................................................................................... 27 4.5.7 Power Failure Management ............................................................................................... 28 4.5.8 Error Detection/Correction.................................................................................................. 28 4.5.9 Special Features Through I/O Control (IOCTL) Mechanism.............................................. 28 4.5.10 Compatibility ....................................................................................................................... 29 4.6 8KB Memory Window ....................................................................................................... 29 5. Register Descriptions ............................................................................................................. 30 5.1 Definition of Terms ........................................................................................................... 30 5.2 Reset Values .................................................................................................................... 30 5.3 No Operation (NOP) Register........................................................................................... 31 5.4 Chip Identification (ID) Register and Chip Identification Confirmation Register [0:1] ....... 31 5 ...

Page 6

Platform-Specific Issues ................................................................................................... 46 7.8.1 Wait State ........................................................................................................................... 46 7.8.2 Big and Little Endian Systems............................................................................................ 46 7.8.3 Busy Signal......................................................................................................................... 46 7.8.4 Working with 8/16/32-Bit Systems...................................................................................... 46 7.9 Design Environment ......................................................................................................... 48 8. Product Specifications ........................................................................................................... 49 8.1 Environmental Specifications ...

Page 7

... Theory of operation for the major building blocks Section 2: Detailed description of hardware protection and security-enabling features Section 3: Detailed description of modes of operation and TrueFFS technology, including Section 4: power failure management and 8KByte memory window mDOC H1 register descriptions Section 5: Overview of how to boot from mDOC H1 Section 6: Hardware and software design considerations ...

Page 8

... H1 is one msystems’ latest developments in industry-leading memory solutions for high- capacity data and code storage. mDOC H1, packed in a small FBGA package with 4Gb (512MB) or 8Gb (1GB) capacity device with an embedded thin flash controller and flash memory. It uses 90 nm process NAND-based flash technology, enhanced by msystems’ advanced x2 technology. ...

Page 9

Standard Interface 1.2.1 Ball Diagram See Figure 1 for the mDOC H1 standard interface ballout. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should either be left floating or connected to the recommended ...

Page 10

Top View RSRVD Figure 1 Standard Interface Ballout for mDOC H1 12x18 ...

Page 11

System Interface See Figure 2 for a simplified I/O diagram for a standard interface of mDOC H1. CE#, OE#, WE# A[12:0] D[15:0] System Interface Figure 2: Standard Interface Simplified I/O Diagram for mDOC H1 11 mDOC H1 IF_CFG ID[1:0] ...

Page 12

... ST Write Enable, active low. Configuration ST Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1 = ID1, ID0 = VSS, VSS (logic 0, logic 0); required for single chip Chip 2 = ID1, ID0 = VSS, VCCQ (logic 0, logic 1) ST Lock, active low. When active, provides full hardware data protection of selected partitions ...

Page 13

Signal Ball No. VCC K5 VCCQ K6 VSS H3, K9 RSRVD K2 D4, D5, E4, E6, E9, F6, F9, J9, NC A1, A2, A9, A10, B1, B2, B9, B10, C2, C3, C4, C5, C6, C7, C8, C9, ...

Page 14

Multiplexed Interface 1.3.1 Ball Diagram See Figure 3 for the mDOC H1 ball diagram. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should either be left floating or connected to the recommended signals. ...

Page 15

Top View RSRVD RSRVD Figure 3: Multiplexed Interface Ballout for mDOC H1 ...

Page 16

System Interface See Figure 4 for a simplified I/O diagram of mDOC H1 multiplexed interface. CE#, OE#, WE# AD[15:0] System Interface Figure 4: Multiplexed Interface Simplified I/O Diagram for mDOC H1 16 mDOC H1 ID0 AVD# LOCK# Configuration Data ...

Page 17

... Output Enable, active low. Configuration ST Set multiplexed interface. ST Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1 = ID0 = VSS, must be used for single-chip configuration. Chip 2 = ID0 = VCCQ ST Lock, active low. When active, provides full hardware data protection of selected partitions. ...

Page 18

Signal Ball No. Type RSRVD H8 K2 D4, D5, E4, E6, E9, F6, F9, H8, J8, L6, NC A1, A2, A9, A10, B1, B2, B9, B10, C2, C3, C4, C5, C6, C7, C8, C9, C10, D1, D2, ...

Page 19

T O HEORY OF PERATION 2.1 Overview mDOC H1 consists of the following major functional blocks, as shown in Figure 5. DATA [15:0] ADDR [12:0] CE#, OE#, WE#, RSTIN# BUSY# IRQ# ID[1:0], IF_CFG, LOCK#, AVD # Figure 5: mDOC ...

Page 20

... Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system initialization. A 13-bit wide address bus enables access to the mDOC H1 8KB memory window (as shown in Section 4.6). The Chip Enable (CE#), Output Enable (OE#) and Write Enable (WE#) signals trigger read and write cycles ...

Page 21

... Read/Write Protection Data and code protection is implemented through a Protection State Machine (PSM). The user can configure an independently programmable area of the flash memory as read protected, write protected, or read/write protected. A protected partition may be protected by either/both of these hardware mechanisms: • 64-bit protection key • ...

Page 22

This feature can be useful when the boot code in the boot partition must be read/write protected. Upon power-up, the boot code must be unprotected so the CPU can boot directly from mDOC. At the end of the boot process, ...

Page 23

H P ARDWARE ROTECTION 3.1 Method of Operation mDOC H1 enables the user to define a partition that is protected (in hardware) against any combination of read or write operations. The protected area can be configured as read protected ...

Page 24

M O ODES OF PERATION mDOC H1 operates in one of three basic modes: • Normal mode • Standby Mode • Reset mode • Deep Power-Down mode The current mode of the chip can always be determined by reading ...

Page 25

... Normal Mode This is the mode in which standard operations involving the flash memory are performed. Normal mode is entered when a valid write sequence is sent to the mDOC Control register and Control Confirmation register. A write cycle occurs when both the CE# and WE# inputs are asserted. ...

Page 26

... TrueFFS Technology 4.5.1 General Description msystems’ patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard disk, making it completely transparent to the OS. In addition, since it operates under the OS file system layer (see Figure 7 completely transparent to the application ...

Page 27

... Wear-Leveling Flash memory can be erased a limited number of times. This number is called the erase cycle limit, or write endurance limit, and is defined by the flash array vendor. The erase cycle limit applies to each individual erase block in the flash device. ...

Page 28

... If wear-leveling were only applied on newly written pages, static areas would never be recycled. This limited application of wear-leveling would lower life expectancy significantly in cases where flash memory contains large static areas. To overcome this problem, TrueFFS forces data transfer in static areas as well as in dynamic areas, thereby applying wear-leveling to the entire media ...

Page 29

... The 1KB Programmable Boot Block is aliased two times in both section 0 and section 3 for redundancy reasons. The addresses described here are relative to the absolute starting address of the 8KB memory window ...

Page 30

R D EGISTER ESCRIPTIONS This section describes various mDOC H1 registers and their functions, as listed in Table 3. Most mDOC H1 registers are 8-bit, unless otherwise denoted as 16-bit. Address (Hex) 1002 1000/1074 1008 100C 1072 100A 100E ...

Page 31

No Operation (NOP) Register Description: An access to this 16-bit register results in no change in the device.. To aid in code readability and documentation, software should access this register when performing cycles intended to create a time delay. ...

Page 32

Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the byte swap ...

Page 33

... After writing the required value to the mDOC H1 Control register, the complement of that data byte must also be written to the Control Confirmation register. The two writes cycles must not be separated by any other read or write cycles to the mDOC H1 memory space, except for reads from the Programmable Boot Block space. Address ...

Page 34

Device ID Select Register Description cascaded configuration, this register controls which device provides the register space. The value of bit ID[0:1] is compared to the value of the ID configuration input balls. The device whose ID input ...

Page 35

Configuration Register Description: This register indicates the current configuration of mDOC H1. Unless otherwise noted, the bits are reset only by a hardware reset, and not upon boot detection or any other entry to Reset mode. Address (hex): 100EH ...

Page 36

Interrupt Control Register Description: This register controls how interrupts are generated by mDOC H1, and indicates which of the following three sources has asserted an interrupt: • Flash array is ready • Data protection violation • Reading or writing ...

Page 37

Output Control Register Description: This register controls the behavior of certain output signals. This register is reset by a hardware reset, not by entering Reset mode. Note: When multiple devices are cascaded, writing to this register will affect all ...

Page 38

B DOC H1 OOTING FROM M 6.1 Introduction mDOC H1 can function both as a flash disk and as the system boot device. If mDOC H1 is configured as a flash disk and as the system boot device, it ...

Page 39

... ESIGN ONSIDERATIONS 7.1 General Guidelines A typical RISC processor memory architecture is shown in Figure 9. It may include the following devices: • mDOC H1: Contains the OS image, applications, registry entries, back-up data, user files and data, etc. It can also be used to perform boot operation, thereby replacing the need for a separate boot device. • ...

Page 40

... Standard NOR-Like Interface mDOC H1 uses a NOR-like interface that can easily be connected to any microprocessor bus. With a standard interface, it requires 13 address lines, 8 data lines and basic memory control signals (CE#, OE#, WE#), as shown in Figure 10 below. Typically, mDOC H1 can be mapped to any free 8KB memory space. ...

Page 41

Multiplexed Interface With a multiplexed interface, mDOC H1 requires the signals shown in Figure 11 below. 41 Figure 11: Multiplexed System Interface Data Sheet, Rev. 1.1 mDOC H1 4Gb (512MByte) and 8Gb (1GByte) 95-DT-1104-01 ...

Page 42

... Chip Enable (CE#) – Connect this signal to the memory address decoder. Most RISC processors include a programmable decoder to generate various Chip Select (CS) outputs for different memory zones. These CS signals can be programmed to support different wait states to accommodate mDOC H1 timing specifications. • Power-On Reset In (RSTIN#) – Connect this signal to the host’s active-low Power-On Reset signal. Note: The reset circuit should be designed to accommodate system specific requirement • ...

Page 43

Implementing the Interrupt Mechanism 7.5.1 Hardware Configuration To configure the hardware for working with the interrupt mechanism, connect the IRQ# ball to the host interrupt input. Note: A nominal 10 KΩ pull-up resistor should be connected to this ball. ...

Page 44

Device Cascading When connecting mDOC H1 using either standard or multiplexed interface two devices can be cascaded with no external decoding circuitry. Figure 12 illustrates the configuration required to cascade two devices on the host bus (only ...

Page 45

Boot Replacement A typical RISC architecture uses a boot ROM for system initialization. The boot ROM is also required to access mDOC H1 during the boot sequence in order to load OS images and the device drivers. msystems’ Boot ...

Page 46

Platform-Specific Issues This section discusses hardware design issues for major embedded RISC processor families. 7.8.1 Wait State Wait states can be implemented only when mDOC H1 is designed in a bus that supports a Wait state insertion, and supplies ...

Page 47

Data Access Mode When configured for 8-bit operation, ball IF_CFG should be connected to VSS, data lines D[15:8] are internally pulled up and may be left unconnected. The device routes odd and even address accesses to the appropriate ...

Page 48

Design Environment mDOC H1 provides a complete design environment consisting of: • Evaluation boards (EVBs) for enabling software integration and development with mDOC H1, even before the target platform is available. • Programming solutions: Programming house o On-board programming ...

Page 49

P S RODUCT PECIFICATIONS 8.1 Environmental Specifications 8.1.1 Operating Temperature Extended temperature range: -30°C to +85°C 8.1.2 Thermal Characteristics Junction to Case (θ 8.1.3 Humidity 10% to 90% relative, non-condensing 8.2 Electrical Specifications 8.2.1 Absolute Maximum Ratings Symbol VCC ...

Page 50

Capacitance Symbol Parameter C Input capacitance IN C Input/Output capacitance IO Notes: 1. The following signals may exceed indicated max capacitance level of 60pF: D5, D6, D7, D14 and IRQ. 8.2.3 DC Electrical Characteristics over Operating ...

Page 51

Symbol Parameter I leakage current LK V High-level output voltage OH V Low-level output voltage OL V Hysteresis HYS I Active supply current CC Active VCCQ supply I ccq current Standby supply current I CCS VCC balls Standby supply current ...

Page 52

Timing Specifications 8.3.1 Read Cycle Timing Standard Interface A[12:0] CE# WE# OE# D[15:0] Figure 15: Standard Interface, Read Cycle Timing t SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 16: Standard Interface, Read Cycle Timing – Asynchronous ...

Page 53

Table 10: Standard Interface Read Cycle Timing Parameters Symbol t Address to OE# ) SU(A t OE# to Address hold time HO( CE# to OE# SU(CE0 OE# to CE# HO(CE0) t OE# to CE# HO(CE1) t ...

Page 54

Write Cycle Timing Standard Interface A[1 2 HO(CE1 D[15:0 ] Figure 17: Standard Interface Write Cycle Timing Table 11: Standard Interface Write Cycle Parameters Symbol Address to WE ...

Page 55

Symbol t WE# to CE# HO(CE1) t CE# to WE# SU(CE1) t WE# to start of next cycle REC(WE WE# t SU( WE# addresses hold time HO(D) Notes: 1. CE# may be ...

Page 56

Read Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] CE# t (CE1) HO OE# WE# Figure 18: Multiplexed Interface Read Cycle Timing Table 12: Multiplexed Interface Read Cycle Parameters Symbol t Address to AVD# SU(AVD) t Address to ...

Page 57

Notes: 1. CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be referenced instead to the time of CE# asserted. 2. CE# may be ...

Page 58

Write Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] t (CE1) HO CE# OE# WE# Figure 19: Multiplexed Interface Write Cycle Timing Table 13: Multiplexed Interface Write Cycle Parameters Symbol t Address to AVD# SU(AVD) t Address to ...

Page 59

... Power-Up Timing mDOC H1 is reset by assertion of the RSTIN# input. When this signal is negated, mDOC H1 initiates a download procedure from the flash memory into the internal Programmable Boot Block. During this procedure, mDOC H1 does not respond to read or write accesses. Host systems must therefore observe the requirements described below for first access to mDOC H1 ...

Page 60

VCC = 2.7V VCCQ = 1.65 or 2.7V VCC RSTIN# BUSY# CE#, OE#, WE# D (Read cycle) Table 14: Power-Up and Reset Timing Parameters Symbol t 1 VCC rise time RISE(VCC VCCQ rise time RISE(VCCQ VCC ...

Page 61

Interrupt Timing IRQ# Symbol Tw(IRQ#) IRQ# asserted pulse width (Edge mode) 61 Tw(IRQ#) Figure 21: IRQ# Pulse Width in Edge Mode Table 15: Interrupt Timing Description Data Sheet, Rev. 1.1 mDOC H1 4Gb (512MByte) and 8Gb (1GByte) Min Max ...

Page 62

Mechanical Dimensions FBGA dimensions: 12.0 ±0. 18.0 ±0. 1.3 ±0.1 mm Ball pitch: 0.8 mm Figure 22: Mechanical Dimensions 12x18 FBGA Package (Bottom View) 62 mDOC H1 4Gb (512MByte) and 8Gb (1GByte ...

Page 63

... RDERING NFORMATION Refer to Table 16 for mDOC H1 products currently available and the associated ordering information. Ordering Information MD2433-d4G-V3Q18-X-P MD2433-d4G-V3Q18-X-P/Y MD2433-d4G-V3Q18-X-P-H MD2433-d4G-V3Q18-X-P-H/Y MD2433-d4G-V3Q18-X-P-T MD2433-d4G-V3Q18-X-P-T/Y MD2433-d8G-V3Q18-X-P MD2433-d8G-V3Q18-X-P/Y MD2433-d00-DAISY MD2433-d00-DAISY-P 63 Table 16: mDOC H1 Available Products Capacity Package MB Gb 512 4 115-ball 12x18 FBGA Pb-free in Tape & Reel ...

Page 64

ONTACT S USA msystems, Inc. 555 North Mathilda Avenue, Suite 220 Sunnyvale, CA 94085 Phone: +1-408-470-4440 Fax: +1-408-470-4470 Japan msystems Japan Inc. Asahi Seimei Gotanda Bldg., 3F 5-25-16 Higashi-Gotanda Shinagawa-ku Tokyo, 141-0022 Phone: +81-3-5423-8101 Fax: ...

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