SDED5-001G-NAT SanDisk, SDED5-001G-NAT Datasheet - Page 9

• Manufacturer Part Number: SDED5-001G-NAT
• Description: IC MDOC H3 1GB FBGA
• Manufacturer: SanDisk

Specifications of SDED5-001G-NAT

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 115-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Rev. 1.3
6. Embedded TrueFFS Technology............................................................................................34
7. mDOC H3 Registers ................................................................................................................40
8. Booting from mDOC H3 ..........................................................................................................47
9. Design Considerations ...........................................................................................................49
9
6.1
6.2
6.3
6.4
6.5
7.1
7.2
7.3
8.1
9.1
9.2
9.3
9.4
General Description ..........................................................................................................34
Operating System Support ...............................................................................................34
DOC Driver Software Development Kit (SDK)..................................................................35
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
128KB Memory Window ...................................................................................................37
8KB Memory Window .......................................................................................................39
Definition of Terms............................................................................................................40
Reset Values ....................................................................................................................40
Registers Description........................................................................................................41
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 DMA Negation Register ......................................................................................................45
7.3.11 Software Lock Register .......................................................................................................45
7.3.12 Endian Control Register ......................................................................................................46
Introduction .......................................................................................................................47
8.1.1
8.1.2
General Guidelines ...........................................................................................................49
Configuration ....................................................................................................................49
Demux (Standard) Interface .............................................................................................49
Multiplexed Interface.........................................................................................................50
File Management ................................................................................................................35
Bad-Block Management......................................................................................................35
Wear-Leveling .....................................................................................................................35
Power Failure Management ................................................................................................36
Error Detection/Correction ..................................................................................................36
Special Features through I/O Control (IOCTL) Mechanism................................................36
Compatibility........................................................................................................................37
Paged RAM Command Register.........................................................................................41
Paged RAM Select Register ...............................................................................................41
Paged RAM Unique ID Download Register ........................................................................42
Chip Identification (ID) Register [0:1] ..................................................................................42
Burst Mode Control Registers (Read & Write) ....................................................................42
Burst Write Mode Exit Register ...........................................................................................43
DPD Wakeup Trigger Register............................................................................................43
DPD Activation Register......................................................................................................44
DMA Control Register .........................................................................................................44
Asynchronous Boot Mode ...................................................................................................48
Paged RAM Boot ................................................................................................................48
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
92-DS-1205-10