SDED5-002G-NCY SanDisk, SDED5-002G-NCY Datasheet - Page 23

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SDED5-002G-NCY

Manufacturer Part Number
SDED5-002G-NCY
Description
IC MDOC H3 2GB FBGA
Manufacturer
SanDisk
Datasheet

Specifications of SDED5-002G-NCY

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
16G (2G x 8)
Interface
Parallel
Voltage - Supply
1.65 V ~ 1.95 V
Operating Temperature
-25°C ~ 85°C
Package / Case
115-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-

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Rev. 1.3
2.
1.
3.
4.
5.
2.3.3
See Figure 5 for a simplified I/O diagram of multiplexed interface mDOC H3. The power
connections and capacitors in this diagram are for illustration only. For detailed
recommendations regarding power connections and required capacitors, please refer to section
9.5.
23
RSRVD
The following abbreviations are used: ST - Schmidt Trigger input. IN/PD – CMOS input with internal pull down resistor (77KΩ to 312KΩ;
135KΩ typical), which is enabled only when the 8KB memory window is in use, ST/PU - Schmitt Trigger input with internal pull up
resistor (95KΩ to 261 KΩ; 149 KΩ typical).
When mDOC H3 is used as a Master device, SO is used for Serial Interface Data In, and SI used for Serial Interface Data Out.
The capacitor is required only for 1.8V Core and 1.8V I/O configuration. Please see section 9.5 for further details.
problems. In order to support this feature, the JTAG balls should be brought out to a separate header or test points. The JTAG RSRVD
balls must not be connected to the JTAG scan chain that is used for the rest of the PCB. If not used they should be left floating.
BUSY#, DMARQ# and IRQ# should not be pulled up to any voltage higher than VCCQ. A pull-up resistor is required if this pin will be
connected to an input. A 10K ohm resistor to Vccq is recommended, however the exact value depends on system power, timing and signal
integrity requirements.
Signal
The RSRVD JTAG balls will only be enabled on special versions of the mDOC H3 devices that will be used for debugging severe system
NC
System Interface
D10, E9, F1,
M2, M3, M4,
A10, B1, B2,
F9, G1, H1,
G5, G6, H5,
C2, C3, C4,
C5, C6, C7,
L2, L9, L10,
M5, M6,M7,
H6, N2, N9,
A1, A2, A9,
J1, K1, K2,
C10, D1,
B9, B10,
N10, P2,
Ball No.
M8, M9,
P9, P10
C8, C9,
D2, D9,
M10
M1
P1
N1
L1
CMOS output Test Data Out (JTAG).
Signal Type
ST/PU
ST/PU
ST/PU
-
-
1
All reserved signals are not connected
internally, and if not identified in this document
then it is recommended to leave them floating
to guarantee forward compatibility with future
products. They should not be connected to
arbitrary signals.
Test Data In (JTAG).
Used for dedicated developer product only
Used for dedicated developer product only
Test Mode Select (JTAG)
Used for dedicated developer product only
Test Clock (JTAG).
Used for dedicated developer product only
Not Connected.
Mechanical
Reserved
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
Description
4
4
4
4
.
.
.
.
Product Overview
Direction
92-DS-1205-10
Signal
Output
Input
Input
Input

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