SDED5-512M-N9Y SanDisk, SDED5-512M-N9Y Datasheet - Page 18

• Manufacturer Part Number: SDED5-512M-N9Y
• Description: IC MDOC H3 4GB 115-FBGA
• Manufacturer: SanDisk

Specifications of SDED5-512M-N9Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 4G (512M x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 115-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Rev. 1.3
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RSRVD
Signal
The following abbreviations are used: ST - Schmitt Trigger input. IN/PD – CMOS input with internal pull down resistor (77KΩ to 312KΩ;
135KΩ typical), which is enabled only when 8KB memory window is in use, ST/PU - Schmitt Trigger input with internal pull up resistor
(95KΩ to 261 KΩ; 149 KΩ typical).
When mDOC H3 is used as a Master device, SO is used for Serial Interface Data In, and SI is used for Serial Interface Data Out.
The capacitor is required only for 1.8V Core and 1.8V I/O configuration. Please see section 9.5 for further details.
The RSRVD JTAG balls will only be enabled on special versions of the mDOC H3 devices that will be used for debugging severe system
problems. In order to support this feature, the JTAG balls should be brought out to a separate header or test points. The JTAG RSRVD
balls must not be connected to the JTAG scan chain that is used for the rest of the PCB. If not used they should be left floating.
BUSY#, DMARQ# and IRQ# should not be pulled up to any voltage higher than VCCQ. A pull-up resistor is required if this pin will be
connected to an input. A 10K ohm resistor to Vccq is recommended, however the exact value depends on system power, timing and signal
integrity requirements.
NC
J1, K1, K2,
C10, D1,
D10, E9,
L10, M2,
N10, P2,
A9, A10,
B9, B10,
Ball No.
M3, M4,
M8, M9,
P9, P10
G1, H1,
G5, G6,
C2, C3,
C4, C5,
C6, C7,
C8, C9,
D2, D9,
M6,M7,
H5, H6,
N2, N9,
A1, A2,
B1, B2,
F1, F9,
L2, L9,
M10
M5,
M1
P1
N1
L1
CMOS output
Signal Type
ST/PU
ST/PU
ST/PU
-
-
1
Mechanical
All reserved signals are not connected
internally, and if not identified in this
document then it is recommended to leave
them floating to guarantee forward
compatibility with future products. They
should not be connected to arbitrary signals,
and must not be connected to GND
Test Data In (JTAG).
Used for dedicated developer product only
Test Data Out (JTAG).
Used for dedicated developer product only
Test Mode Select (JTAG)
Used for dedicated developer product only
Test Clock (JTAG).
Used for dedicated developer product only
Not Connected.
Reserved
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
Description
4
4
4
4
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Product Overview
92-DS-1205-10
Direction
Signal
Output
Input
Input
Input