SDED5-512M-N9Y SanDisk, SDED5-512M-N9Y Datasheet - Page 77

• Manufacturer Part Number: SDED5-512M-N9Y
• Description: IC MDOC H3 4GB 115-FBGA
• Manufacturer: SanDisk

Specifications of SDED5-512M-N9Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 4G (512M x 8)
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 115-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

Rev. 1.3
10.3.11
When operating mDOC H3 with separate power supplies powering the VCCQ, VCC, VCC1 or
VCC2 rails, it is desirable to turn the supplies on and off simultaneously. Providing power to one
supply rail and not the other (either at power-on or power-off) can cause excessive power
dissipation. Damage to the device may result if this condition persists for more than 500 msec.
10.3.12
mDOC H3 is reset by assertion of the RSTIN# input. When this signal is negated, mDOC H3
initiates a download procedure from the flash memory into the internal Programmable Boot
Block. During this procedure, mDOC H3 does not respond to read or write access.
Host systems must therefore observe the requirements described below for initial access to
mDOC H3. Any of the following methods may be employed to guarantee first-access timing
requirements:
Hosts that use mDOC H3 to boot the system must employ the latter option or use another method
to guarantee the required timing of initial access.
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• Use a software loop to wait at least Tp (BUSY1) before accessing the device after the
• Poll the state of the BUSY# output.
• Use the BUSY# output to hold the host CPU in wait state before initiating the first access
reset signal is negated.
which will be a RAM read cycle. At least one of the signals CE# and OE# must be kept
negated (high) until BUSY# is negated.
Power Supply Sequence
Power-Up Timing
Figure 33: Slave SPI Control Timing
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
Product Specifications
92-DS-1205-10