EPC2TI32N Altera, EPC2TI32N Datasheet - Page 9

• Manufacturer Part Number: EPC2TI32N
• Description: IC CONFIG DEVICE 1.6MBIT 32-TQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC2TI32N

• Programmable Type: In System Programmable
• Memory Size: 1.6Mb
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1648

Chapter 4: Configuration Devices for SRAM-Based LUT Devices Data Sheet
Power and Operation
Power and Operation
Power-On Reset (POR)
Error Detection Circuitry
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Altera Corporation
low, which in turn drives the target device’s nSTATUS pin low. Configuration
automatically restarts if the Auto-restart configuration on error option is turned on in
the Quartus II software from the General tab of the Device & Pin Options dialog box
or the MAX+PLUS II software’s Global Project Device Options dialog box (Assign
menu).
For more information about FPGA configuration and configuration interface
connections between configuration devices and Altera FPGAs, refer to the
appropriate FPGA family chapter in the
This section describes Power-On Reset (POR) delay, error detection, and 3.3-V and
5.0-V operation of Altera configuration devices.
During initial power-up, a POR delay occurs to permit voltage levels to stabilize.
When configuring an FPGA with an EPC1, EPC2, or EPC1441 device, the POR delay
occurs inside the configuration device, and the POR delay is a maximum of 200 ms.
When configuring a FLEX 8000 device with an EPC1213, EPC1064, or EPC1064V
device, the POR delay occurs inside the FLEX 8000 device, and the POR delay is
typically, 100 ms, with a maximum of 200 ms.
During POR, the configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target FPGA’s nSTATUS pin.
When the configuration device completes POR, it releases its open-drain OE pin,
which is then pulled high by a pull-up resistor.
The FPGA should be powered up before the configuration device exits POR to avoid
the master configuration device from entering slave mode.
If the FPGA is not powered up before the configuration device exits POR, the
CONF_DONE/nCS line will be high because of the pull-up resistor. When the
configuration device exits POR and releases OE, it sees nCS high, which signals the
configuration device to enter slave mode. Therefore, configuration will not begin (the
DATA output is tri-stated and DCLK is an input pin in slave mode).
The EPC1, EPC2, and EPC1441 configuration devices have built-in error detection
circuitry for configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone,
Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, or
Stratix II GX devices.
Built-in error-detection circuitry uses the nCS pin of the configuration device, which
monitors the CONF_DONE pin on the FPGA. If nCS on the master EPC1 or EPC2 device
is driven high before all configuration data is transferred, the master EPC1 or EPC2
device drives its OE signal low, which in turn drives the FPGA’s nSTATUS pin low,
indicating a configuration error. Additionally, if the configuration device sends is
generated its data and detects that CONF_DONE has not gone high, it recognizes that
the FPGA has not configured successfully. EPC1 and EPC2 devices wait for 16 DCLK
Configuration
Configuration Handbook (Complete Two-Volume Set)
Handbook.
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