AT17LV128-10JC Atmel, AT17LV128-10JC Datasheet
AT17LV128-10JC
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AT17LV128-10JC Summary of contents
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... Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. ® ® ™ FLEX , APEX ® ® , Virtex FPGAs Table 1-1. The AT17LV series FPGA Configuration EEPROM Memory AT17LV65 AT17LV128 AT17LV256 AT17LV512 AT17LV010 AT17LV002 AT17LV040 3.3V and 5V System Support 2321I–CNFG–2/08 ...
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... LAP 8-lead PDIP 8-lead SOIC 20-lead PLCC 20-lead SOIC 44-lead TQFP Notes: 2. Pin Configuration Figure 2-1. Figure 2-2. Figure 2-3. AT17LV65/128/256/512/010/002/040 2 AT17LV Series Packages AT17LV65/ AT17LV128/ AT17LV512/ AT17LV256 AT17LV010 Yes Yes Yes Yes Use 8-lead Yes LAP Yes Yes (2) Yes Yes – ...
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Figure 2-4. Notes: Figure 2-5. Note: 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 20-lead PLCC CLK 4 (2) (WP1 ) NC 5 (1) (WP ) RESET/OE 6 (2) (WP2 ) This pin is only available on AT17LV65/128/256 devices. 2. This ...
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Figure 2-6. Notes: Figure 2-7. Note: AT17LV65/128/256/512/010/002/040 4 (1) 20-lead SOIC DATA CLK RESET/ This pinout only applies to AT17LV512/010/002 devices. 2. ...
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Figure 2-8. Block Diagram SER_EN (2) WP1 (2) WP2 POWER ON RESET Notes: 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the ...
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... DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 4. Pin Description AT17LV65/ AT17LV128/ AT17LV256 8 DIP/ LAP/ 20 ...
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DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 4.2 CLK Clock input. Used to increment the internal address and bit counter for reading and programming. 4.3 WP1 WRITE PROTECT (1). Used to protect portions of memory ...
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... FPGA mode pins. In Master mode, the FPGA automatically loads the config- uration program from an external memory. The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xil- inx applications. 6. Control of Configuration Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory ...
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Cascading Serial Configuration EEPROMs For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator ...
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Absolute Maximum Ratings* Operating Temperature................................... -40° +85° C Storage Temperature .................................... -65° +150° C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering ...
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... Supply Current, Standby Mode CCS 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 AT17LV65/ AT17LV128/ AT17LV256 Min 2 -2.5 mA) 2.4 Commercial = +3 mA mA) 2.4 Industrial = +3 mA GND) - Commercial Industrial AT17LV65/ AT17LV128/ AT17LV256 Min 2 -2.5 mA) 3.7 Commercial = +3 mA mA) 3.6 Industrial = +3 mA GND) - Commercial Industrial AT17LV512/ AT17LV002/ AT17LV010 AT17LV040 Max Min ...
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AC Waveforms CE RESET/OE CLK T CE DATA 16. AC Waveforms when Cascading RESET/OE CE CLK T DATA LAST BIT T CEO AT17LV65/128/256/512/010/002/040 12 T SCE CAC CDF T OCK OCE T ...
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AC Characteristics V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK ...
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AC Characteristics ± 5% Commercial ± 10% Industrial CC CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC ...
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... Thin Plastic Quad Flat 44A Package (TQFP) Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 (1) AT17LV65/ AT17LV128/ AT17LV512/ AT17LV256 AT17LV010 θ [° C/ θ JA 115.71 (2) [° ...
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... Plastic J-leaded Chip Carrier (PLCC) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) AT17LV65/128/256/512/010/002/040 16 AT17LV65A-10PC Special Pinouts = 65K A = Altera = 128K Blank = Xilinx /Atmel/ Other = 256K = 512K = Package Type Package Temperature C = 8CN4 C = Commercial ...
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... For the -10SC and -10SI packages, customers may migrate to the AT17LVXXX-10SU. 3. For the -10TQC and -10TQI packages, customers may migrate to the AT17LVXXX-10TQU. 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 Ordering Code AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI ...
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Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size (1) 256-Kbit (1) 512-Kbit (1) 1-Mbit (1) 2-Mbit AT17LV002-10TQU (1) 4-Mbit AT17LV040-10TQU Note: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. AT17LV65/128/256/512/010/002/040 18 Ordering Code ...
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... TYP Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm Package Drawing Contact: packagedrawings@atmel.com 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 D Pin1 Corner TITLE 8CN4, 8-lead ( 1.04 mm Body), Lead Pitch 1.27mm, ...
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PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with ...
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SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 ...
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PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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SOIC 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 23 ...
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TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per ...
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Revision History Revision Level – Release Date H – March 2006 I – February 2008 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 History Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI. Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information. 25 ...
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