XCF02SVO20C Xilinx Inc, XCF02SVO20C Datasheet

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XCF02SVO20C

Manufacturer Part Number
XCF02SVO20C
Description
IC PROM IN SYST PRG 3.3V 20TSSOP
Manufacturer
Xilinx Inc
Datasheet

Specifications of XCF02SVO20C

Programmable Type
In System Programmable
Memory Size
2Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP (0.173", 4.40mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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DS123 (v2.18) May 19, 2010
Features
Description
Xilinx introduces the Platform Flash series of in-system
programmable configuration PROMs. Available in
1 to 32 Mb densities, these PROMs provide an easy-to-use,
cost-effective, and reprogrammable method for storing large
Xilinx FPGA configuration bitstreams. The Platform Flash
PROM series includes both the 3.3V XCFxxS PROM and
the 1.8V XCFxxP PROM. The XCFxxS version includes
4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial
and Slave Serial FPGA configuration modes
page
Table 1: Platform Flash PROM Features
© Copyright 2003–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS123 (v2.18) May 19, 2010
Product Specification
Notes:
1.
XCF01S
XCF02S
XCF04S
XCF08P
XCF16P
XCF32P
Device
In-System Programmable PROMs for Configuration of
Xilinx® FPGAs
Low-Power Advanced CMOS NOR Flash Process
Endurance of 20,000 Program/Erase Cycles
Operation over Full Industrial Temperature Range
(–40°C to +85°C)
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
JTAG Command Initiation of Standard FPGA
Configuration
Cascadable for Storing Longer or Multiple Bitstreams
Dedicated Boundary-Scan (JTAG) I/O Power Supply (V
I/O Pins Compatible with Voltage Levels Ranging From
1.8V to 3.3V
Design Support Using the Xilinx ISE® Alliance and
Foundation™ Software Packages
XCF08P supports storage of a design revision only when cascaded with another XCFxxP PROM. See
2). The XCFxxP version includes 32 Mb, 16 Mb, and
Density
(Mb)
16
32
1
2
4
8
V
CCINT
3.3
3.3
3.3
1.8
1.8
1.8
(V)
V
CCO
1.8 – 3.3
1.8 – 3.3
1.8 – 3.3
1.8 – 3.3
1.8 – 3.3
1.8 – 3.3
(V)
R
Range
35
V
CCJ
2.5 – 3.3
2.5 – 3.3
2.5 – 3.3
2.5 – 3.3
2.5 – 3.3
2.5 – 3.3
(V)
Range
(Figure 1,
VO20/VOG20
VO20/VOG20
VO20/VOG20
VO48/VOG48
VO48/VOG48
VO48/VOG48
Platform Flash In-System Programmable
FS48/FSG48
FS48/FSG48
FS48/FSG48
Packages
www.xilinx.com
CCJ
)
8 Mb PROMs that support Master Serial, Slave Serial,
Master SelectMAP, and Slave SelectMAP FPGA
configuration modes
When driven from a stable, external clock, the PROMs can
output data at rates up to 33 MHz. Refer to
Characteristics," page 16
A summary of the Platform Flash PROM family members
and supported features is shown in
Program In-system
XCF01S/XCF02S/XCF04S
XCF08P/XCF16P/XCF32P
via JTAG
3.3V Supply Voltage
Serial FPGA Configuration Interface
Available in Small-Footprint VO20 and VOG20
Packages
1.8V Supply Voltage
Serial or Parallel FPGA Configuration Interface
Available in Small-Footprint VOG48, FS48, and
FSG48 Packages
Design Revision Technology Enables Storing and
Accessing Multiple Design Revisions for
Configuration
Built-In Data Decompressor Compatible with Xilinx
Advanced Compression Technology
Config.
Serial
Configuration PROMs
(Figure 2, page
"Design Revisioning," page 8
for timing considerations.
Parallel
Config.
Revisioning
Table
Product Specification
Design
2).
(1)
1.
"AC Electrical
Compression
for details.
1

XCF02SVO20C Summary of contents

Page 1

R DS123 (v2.18) May 19, 2010 Features • In-System Programmable PROMs for Configuration of Xilinx® FPGAs • Low-Power Advanced CMOS NOR Flash Process • Endurance of 20,000 Program/Erase Cycles • Operation over Full Industrial Temperature Range (–40°C to +85°C) • ...

Page 2

R X-Ref Target - Figure 1 CLK TCK Control TMS and JTAG TDI Interface TDO CF Figure 1: XCFxxS Platform Flash PROM Block Diagram X-Ref Target - Figure 2FI CLK CE OSC Control TCK and TMS TDI JTAG TDO Interface ...

Page 3

R See UG161, Platform Flash PROM User Guide, for detailed guidelines on PROM-to-FPGA configuration hardware connections, for software usage, for a reference list of Xilinx FPGAs, and for the respective compatible Platform Flash PROMs. Table 2 lists the Platform Flash ...

Page 4

R Design Security The Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features to fully protect the FPGA programming data against unauthorized reading via JTAG. The XCFxxP PROMs can also be programmed to prevent inadvertent writing via ...

Page 5

R IEEE 1149.1 Boundary-Scan (JTAG) The Platform Flash PROM family is compatible with the IEEE 1149.1 Boundary-Scan standard and the IEEE 1532 in- system configuration standard. A Test Access Port (TAP) and registers are provided to support all required Boundary-Scan ...

Page 6

R Table 6: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence IR[7:5] TDI → Reserved Table 7: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence IR[15:9] IR[8:7] TDI ...

Page 7

R Platform Flash PROM TAP Characteristics The Platform Flash PROM family performs both in-system programming and IEEE 1149.1 Boundary-Scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to ...

Page 8

R Additional Features for the XCFxxP Internal Oscillator The 8/16/32 Mb XCFxxP Platform Flash PROMs include an optional internal oscillator which can be used to drive the CLKOUT and DATA pins on FPGA configuration interface. The internal oscillator can be ...

Page 9

R • Because of the 8 Mb minimum size requirement for each revision, a single 16 Mb PROM can only store up to two separate design revisions: one 16 Mb design revision, one 8 Mb design revision, or two 8 ...

Page 10

R X-Ref Target - Figure 5 PROM 0 REV 0 (8 Mbits) REV 1 (8 Mbits) REV 2 (8 Mbits) REV 3 (8 Mbits) 4 Design Revisions (a) Design Revision storage examples for a single XCF32P PROM PROM 0 REV ...

Page 11

R Reset and Power-On Reset Activation At power up, the device requires the V monotonically rise to the nominal operating voltage within the specified V rise time. If the power supply cannot CCINT meet this requirement, then the device might ...

Page 12

R Standby Mode The PROM enters a low-power standby mode whenever CE is deasserted (High). In standby mode, the address counter is reset, CEO is driven High, and the remaining outputs are placed in a high-impedance state regardless of the ...

Page 13

R DC Electrical Characteristics Absolute Maximum Ratings Symbol Description V Internal supply voltage relative to GND CCINT V I/O supply voltage relative to GND CCO V JTAG I/O supply voltage relative to GND CCJ V Input voltage with respect to ...

Page 14

R Recommended Operating Conditions Symbol Description V Internal voltage supply CCINT V 3.3V Operation CCO Supply voltage for output 2.5V Operation drivers 1.8V Operation V Supply voltage 3.3V Operation CCJ for JTAG output 2.5V Operation drivers V 3.3V Operation IL ...

Page 15

R DC Characteristics Over Operating Conditions Symbol Description High-level output voltage for 3.3V outputs High-level output voltage for 2.5V outputs V OH High-level output voltage for 1.8V outputs Low-level output voltage for 3.3V outputs V Low-level output voltage for 2.5V ...

Page 16

R AC Electrical Characteristics AC Characteristics Over Operating Conditions XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock Source X-Ref Target - Figure 7 T SCE CE OE/RESET CLK BUSY T OE (optional DATA ...

Page 17

R Symbol Description (6) Clock period (serial mode) when V (6) Clock period (serial mode) when V T CYC (6) Clock period (parallel mode) when V (6) Clock period (parallel mode) when V (3) CLK Low time when V T ...

Page 18

R XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source X-Ref Target - Figure 8 CE OE/RESET CLK CLKOUT T CECC T OECC BUSY T OE (optional DATA CFCC T HCF CF ...

Page 19

R Symbol (7) Clock period (serial mode) when V (7) Clock period (serial mode) when V T CYCO (7) Clock period (parallel mode) when V (7) Clock period (parallel mode) when V (3) CLK Low time when ...

Page 20

R Symbol EN_EXT_SEL hold time from CF, CE, or OE/RESET when V T HXT EN_EXT_SEL hold time from CF, CE, or OE/RESET when V REV_SEL setup time to CF, CE, or OE/RESET when V T SRV REV_SEL setup time to ...

Page 21

R XCFxxP PROM as Configuration Master with Internal Oscillator as Clock Source X-Ref Target - Figure 9 CE OE/RESET CLKOUT T CEC T OEC BUSY T OE (optional DATA CFC T HCF CF EN_EXT_SEL T ...

Page 22

R Symbol BUSY setup time to CLKOUT when BUSY setup time to CLKOUT when V BUSY hold time to CLKOUT when BUSY hold time to CLKOUT when V ( CLKOUT delay when ...

Page 23

R AC Characteristics Over Operating Conditions When Cascading X-Ref Target - Figure 10 OE/RESET CE CLK CLKOUT (optional) DATA CEO Symbol Description CLK to output float delay when V = 2.5V or 3.3V T CCO CDF CLK to output float ...

Page 24

R Pinouts and Pin Descriptions The XCFxxS Platform Flash PROM is available in the VO20 and VOG20 packages. The XCFxxP Platform Flash PROM is available in the VO48, VOG48, FS48, and FSG48 packages. For package drawings, specifications, and additional information, ...

Page 25

R Table 12: XCFxxS Pin Names and Descriptions (Cont’d) Boundary Boundary-Scan Pin Name Scan Order Function TDO – Data Out VCCINT – VCCO – VCCJ – GND – DNC – XCFxxS VO20/VOG20 Pinout Diagram X-Ref Target - Figure 11 D0 ...

Page 26

R XCFxxP Pinouts and Pin Descriptions XCFxxP VO48/VOG48 and FS48/FSG48 Pin Names and Descriptions Table 13 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48 packages. Table 13: XCFxxP Pin Names and ...

Page 27

R Table 13: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Cont’d) Boundary- Boundary- Pin Name Scan Scan Order Function 06 Data Out CEO 05 Output Enable EN_EXT_SEL 31 Data In REV_SEL0 30 Data In REV_SEL1 29 Data In BUSY ...

Page 28

R Table 13: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Cont’d) Boundary- Boundary- Pin Name Scan Scan Order Function VCCINT – VCCO – VCCJ – GND – DNC – XCFxxP VO48/VOG48 Pinout Diagram X-Ref Target - Figure 12 DNC ...

Page 29

R XCFxxP FS48/FSG48 Pin Names Table 14: XCFxxP Pin Names (FS48/FSG48) Pin Pin Pin Name Number Number A1 GND E1 A2 GND E2 A3 OE/RESET E3 A4 DNC VCCINT F1 B2 VCCO ...

Page 30

... XCF16P XCF32P Package Type VO48 = 48-pin TSOP Package VOG48 = 48-pin TSOP Package, Pb-free FS48 = 48-pin TFBGA Package FSG48 = 48-pin TFBGA Package, Pb-free Valid Ordering Combinations XCF01SVO20C XCF08PFS48C XCF02SVO20C XCF16PFS48C XCF04SVO20C XCF32PFS48C Marking Information Device Number XCF01S XCF02S XCF04S Package Type XCF08P ...

Page 31

R Figure 14 through Figure 16 illustrate the part markings for each available package. Note: Package types can differ from the samples shown. X-Ref Target - Figure 14 Device Number Xilinx Logo X-Ref Target - Figure 15 TSOP Pin 1 ...

Page 32

R Revision History The following table shows the revision history for this document. Date Version 04/29/03 1.0 Xilinx Initial Release. 06/03/03 1.1 Made edits to all pages. 11/05/03 2.0 Major revision. 11/18/03 2.1 Pinout corrections as follows: • • • ...

Page 33

R Date Version 07/20/04 2.4 • Added Pb-free package options VOG20, FSG48, and VOG48. • • Section • 10/18/04 2.5 • • • • Table • Table • Table • Table 03/14/05 2.6 • Added Virtex-4 LX/FX/SX configuration data to ...

Page 34

R Date Version 12/29/05 2.8 • Notes for (Cont’d) • Enhanced description under section • Enhanced description on design revision sampling under section • Figure 4 and Figure 5 renamed to • Value for • Block diagram in 05/09/06 2.9 ...

Page 35

R Date Version 10/26/09 2.17 • Updated text in second and third bulleted items in (Cont’d) • Removed all references to 1.5V operation from 05/19/10 2.18 Removed ordering codes for discontinued VO48 package from XCN09030). Added note to XCN08005). Notice ...

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