ICE3A1065L Infineon Technologies, ICE3A1065L Datasheet - Page 10

• Manufacturer Part Number: ICE3A1065L
• Description: IC OFFLINE CTRLR SMPS CM 8DIP
• Manufacturer: Infineon Technologies
• Series: CoolSET®F3r

Specifications of ICE3A1065L

• Output Isolation: Isolated
• Frequency Range: 92 ~ 108kHz
• Voltage - Input: 8.5 ~ 22 V
• Voltage - Output: 650V
• Power (watts): 32W
• Operating Temperature: -25°C ~ 130°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ICE3A1065LX; ICE3A1065LXK; SP000098668

3.5
Figure 9
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
internal CoolMOS™ is sensed via an external sense
resistor R
is transformed to a sense voltage V
into the pin CS. If the voltage V
internal threshold voltage V
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the internal CoolMOS™ in case of Current
Limiting. The influence of the AC input voltage on the
maximum output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
A further comparator C11 is implemented to detect
dangerous current levels which could occur if there is a
Version 2.0
PWM Latch
FF1
PWM-OP
Active Burst
Mode
Sense
G10
Current Limiting
&
Latched Off
Current Limiting Block
Propagation-Delay
. By means of R
Mode
Compensation
CS
Blanking
C10
C12
190ns
Spike
csth
Sense
10k
0.257V
the comparator C10
V
D1
csth
Sense
the source current
C11
Sense
Current Limiting
Blanking
Leading
exceeds the
220ns
Edge
which is fed
1pF
1.66V
10
short winding in the transformer or the secondary diode
is shorten. To ensure that there is no accidentally
entering of the Latched Mode by the comparator C11 a
spike blanking with 190ns is integrated in the output
path of comparator C11.
3.5.1
Figure 10
Each time when the internal CoolMOS™ is switched
on, a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. This spike can cause the gate
drive to switch off unintentionally. To avoid a premature
termination of the switching pulse, this spike is blanked
out with a time constant of t
time, the gate drive will not be switched off.
3.5.2
In case of overcurrent detection, the switch-off of the
internal CoolMOS™ is delayed due to the propagation
delay of the circuit. This delay causes an overshoot of
the peak current I
dt of the peak current (see Figure 11).
Figure 11
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
the overshoot dependency on dI/dt of the rising primary
I
I
I
peak2
peak1
Limit
V
csth
V
I
Sense
Sense
Propagation Delay Compensation
Leading Edge Blanking
Leading Edge Blanking
Current Limiting
I
Overshoot2
peak
Signal2
which depends on the ratio of dI/
Functional Description
t
LEB
= 220ns
LEB
CoolSET™-F3
= 220ns. During this
Signal1
t
ICE3xxx65L
Propagation Delay
8 May 2006
I
Overshoot1
t
t