ICE3B1565J Infineon Technologies, ICE3B1565J Datasheet - Page 10

• Manufacturer Part Number: ICE3B1565J
• Description: IC OFFLINE CTRLR SMPS OTP 8DIP
• Manufacturer: Infineon Technologies
• Series: CoolSET®F3r

Specifications of ICE3B1565J

• Output Isolation: Isolated
• Frequency Range: 58 ~ 76kHz
• Voltage - Input: 10.3 ~ 27 V
• Voltage - Output: 650V
• Power (watts): 42W
• Operating Temperature: -25°C ~ 130°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Outputs: 1
• Duty Cycle (max): 80 %
• Output Voltage: 650 V
• Output Current: 1500 mA
• Mounting Style: Through Hole
• Switching Frequency: 74.5 KHz
• Maximum Operating Temperature: + 150 C
• Fall Time: 30 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 30 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ICE3B1565JX; ICE3B1565JXK; SP000098876

3.5
Figure 8
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
integrated Depl. CoolMOS™ is sensed via an external
sense resistor R
current is transformed to a sense voltage V
is fed into the pin CS. If the voltage V
internal threshold voltage V
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the integrated internal CoolMOS™ in case of
Current Limiting. The influence of the AC input voltage
on the maximum output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.32V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
Version 2.4
PWM Latch
FF1
PWM-OP
Active Burst
Mode
G10
Current Limiting
&
Propagation-Delay
Current Limiting
Compensation
Sense
CS
. By means of R
C10
C12
csth
10kΩ
0.32V
the comparator C10
V
D1
csth
Current Limiting
Sense
Sense
Blanking
Leading
220ns
Edge
1pF
exceeds the
the source
Sense
which
10
3.5.1
Figure 9
Each time when the integrated internal CoolMOS™ is
switched on a leading edge spike is generated due to
the primary-side capacitances and secondary-side
rectifier reverse recovery time. This spike can cause
the gate drive to switch off unintentionally. To avoid a
premature termination of the switching pulse, this spike
is blanked out with a time constant of t
During this time, the gate drive will not be switched off.
3.5.2
In case of overcurrent detection, the switch-off of the
integrated internal CoolMOS™ is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current I
the ratio of dI/dt of the peak current (see Figure 10).
Figure 10
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
the overshoot dependency on dI/dt of the rising primary
current. That means the propagation delay time
between exceeding the current sense threshold V
and the switch off of the integrated inernal CoolMOS™
is compensated over temperature within a wide range.
I
I
I
peak2
peak1
Limit
V
csth
I
V
Sense
Sense
Propagation Delay Compensation
Leading Edge Blanking
Leading Edge Blanking
Current Limiting
I
Overshoot2
Signal2
t
LEB
= 220ns
peak
CoolSET™-F3
Signal1
which depends on
ICE3Bxx65J
t
Propagation Delay
14 Nov 2006
LEB
I
Overshoot1
= 220ns.
t
t
csth