ICE3B1565J Infineon Technologies, ICE3B1565J Datasheet - Page 9

• Manufacturer Part Number: ICE3B1565J
• Description: IC OFFLINE CTRLR SMPS OTP 8DIP
• Manufacturer: Infineon Technologies
• Series: CoolSET®F3r

Specifications of ICE3B1565J

• Output Isolation: Isolated
• Frequency Range: 58 ~ 76kHz
• Voltage - Input: 10.3 ~ 27 V
• Voltage - Output: 650V
• Power (watts): 42W
• Operating Temperature: -25°C ~ 130°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Outputs: 1
• Duty Cycle (max): 80 %
• Output Voltage: 650 V
• Output Current: 1500 mA
• Mounting Style: Through Hole
• Switching Frequency: 74.5 KHz
• Maximum Operating Temperature: + 150 C
• Fall Time: 30 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 30 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ICE3B1565JX; ICE3B1565JXK; SP000098876

3.4
Figure 6
3.4.1
The oscillator generates a fixed frequency with
frequency jittering of ±4% from the fixed frequency
(which is ±2.7kHz from 67kHz) at a jittering period T
The switching frequency is f
A resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D
Once the Soft Start period is over and when the IC goes
into normal mode, the Soft Start capacitor will be
charged and discharged through internal current
source, I
jittering period T
Soft Start capacitor, C
T
where k
eg. T
Version 2.4
FJ
Comparator
Comparator
SoftS
Soft Start
= k
Current
Limiting
PWM
FJ
Frequency
FJ
Oscillator
= 4 ms if C
FJ
Clock
Cycle
Jitter
Duty
* C
max
FJ
is a constant = 4 ms/uF
PWM Section
Oscillator and Jittering
to generate a triangular waveform with a
SoftS
PWM Section
FJ
SoftS
which is externally adjustable by the
0.75
SoftS
= 1uF
G8
1
(See Figure 4).
switch
S
R
FF1
= 67kHz.
Q
PWM Section
Gate Driver
G9
&
Gate
max
=0.75.
FJ
.
9
3.4.2
The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the internal CoolMOS™
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator or
the Current-Limit comparator. In case of resetting the
driver is shut down immediately.
3.4.3
The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents.
The Gate Driver is active low at voltages below the
undervoltage lockout threshold V
Figure 7
PWM-Latch
Gate Driver
PWM-Latch FF1
Gate Driver
Gate Driver
1
VCC
CoolSET™-F3
VCCoff
ICE3Bxx65J
Gate
Depl. CoolMOS™
.
14 Nov 2006