LT1579CS8-3.3 Linear Technology, LT1579CS8-3.3 Datasheet - Page 12

• Manufacturer Part Number: LT1579CS8-3.3
• Description: IC LDO REG SMART DUAL 3.3V 8SOIC
• Manufacturer: Linear Technology

Specifications of LT1579CS8-3.3

• Function: Back-Up Management
• Battery Type: Smart Batteries
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LT1579
APPLICATIONS
Device Overview
The LT1579 is a dual input, single output, low dropout
linear regulator. The device is designed to provide an
uninterruptible output voltage from two independent input
voltage sources on a priority basis. All of the circuitry
needed to switch smoothly and automatically between
inputs is incorporated in the device. All power supplied to
the load is drawn from the primary input (V
device senses that the primary input is failing. At this point
the LT1579 smoothly switches from the primary input to
the secondary input (V
The device is capable of providing 300mA from either
input at a dropout voltage of 0.4V. Total quiescent current
when operating from the primary input is 50 A, which is
45 A from the primary input, 2 A from the secondary and
a minimum input current of 3 A which will be drawn from
the higher of the two input voltages.
A single error amplifier controls both output stages so
regulation remains tight regardless of which input is
providing power. Threshold levels for the error amplifier
and low-battery detectors are set by the internal 1.5V
reference. Output voltage is set by an internal resistor
divider for fixed voltage parts and an external divider for
adjustable parts. Internal bias circuitry powers the refer-
ence, error amplifier, output driver controls, logic flags
and low-battery comparators.
The LT1579 aids power management with the use of two
independent low-battery comparators and two status flags.
The low-battery comparators can be used to monitor the
input voltage levels. The BACKUP flag signals when any
power is being drawn from the secondary input and the
DROPOUT flag provides indication that both input volt-
ages are critically low and the output is unregulated.
Additionally, the switch to the secondary input from the
primary can be forced externally through the use of the
secondary select pin (SS). This active low logic pin, when
pulled below the threshold, will cause power draw to
switch from the primary input to the secondary input.
Current flowing in the primary input is reduced to only a
few microamperes, while all power draw (load current and
bias currents) switches to the secondary. The LT1579 has
a low power shutdown state which shuts off all bias
12
U
IN2
INFORMATION
) to maintain output regulation.
U
W
IN1
U
) until the
currents and logic functions. In shutdown, quiescent
currents are 2 A from the primary input, 2 A from the
secondary input and an additional 3 A which is drawn
from the higher of the two input voltages.
Adjustable Operation
The adjustable version of the LT1579 has an output
voltage range of 1.5V to 20V. The output voltage is set by
the ratio of two external resistors as shown in Figure 1. The
device servos the output to maintain the voltage at the
adjust pin at 1.5V. The current in R1 is then equal to 1.5V/
R1 and the current in R2 is the current in R1 minus the
adjust pin bias current. The adjust pin bias current, 6nA at
25 C, flows out of the adjust pin through R1 to ground. The
output voltage can now be calculated using the formula:
The value of R1 should be less than 500k to minimize the
error in the output voltage caused by adjust pin bias
current. With 500k resistors for both R1 and R2, the error
induced by adjust pin bias current at 25 C is 3mV or 0.1%
of the total output voltage. With appropriate value and
tolerance resistors, the error due to adjust pin bias current
may often be ignored. Note that in shutdown, the output is
turned off and the divider current is zero. The parallel
combination of R1 and R2 should be greater than 20k to
allow the error amplifier to start. In applications where the
minimum parallel resistance requirement cannot be met,
a 20k resistor may be placed in series with the adjust pin.
This introduces an error in the reference point for the
resistor divider equal to (I
V
OUT
1 5 1
.
GND
V
Figure 1. Adjustable Operation
OUT
ADJ
R
R
2
1
–
ADJ
R2
R1
I
ADJ
)(20k).
C
R
FB
2
+
C
1579 • F01
OUT
V
OUT