PCF8562TT/2,118 NXP Semiconductors, PCF8562TT/2,118 Datasheet - Page 16
![IC LCD DRIVER 32/128SEG 48-TSSOP](/photos/6/50/65054/568-48-tssop_sot480-1_sml.jpg)
PCF8562TT/2,118
Manufacturer Part Number
PCF8562TT/2,118
Description
IC LCD DRIVER 32/128SEG 48-TSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.PCF8562TT2118.pdf
(37 pages)
Specifications of PCF8562TT/2,118
Package / Case
48-TSSOP
Display Type
LCD
Configuration
7 Segment + DP, 14 Segment (32 Segment)
Interface
I²C
Current - Supply
32µA
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Digits
16
Number Of Segments
32
Maximum Clock Frequency
2640 Hz
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 85 C
Attached Touch Screen
No
Maximum Supply Current
20 uA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
OM6292 - DEMO BOARD PCA2125 RTCOM10088 - KIT FOR LCD DEMO LPC900622-1003 - KIT FOR LCD DEMO
Digits Or Characters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-2029-2
PCF8562TT/2,518
PCF8562TT/2-T
PCF8562TT/2,518
PCF8562TT/2-T
Fig 10. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I
drive mode
multiplex
multiplex
multiplex
x = data bit unchanged.
static
1:2
1:3
1:4
S
S
S
S
S
S
S
S
S
S
S
S
S
n+2
n+3
n+4
n+5
n+6
n
n+1
n+2
n+3
n+1
n+2
n
n+1
LCD segments
e
e
e
e
f
f
f
f
d
d
d
d
g
g
g
g
a
a
a
a
c
c
c
c
b
b
b
b
S
S
S
S
n+1
n
n+7
n
DP
DP
DP
DP
BP1
BP0
BP1
BP0
BP0
BP0
LCD backplanes
BP1
BP2
BP2
BP3
rows/backplane
rows/backplane
rows/backplane
rows/backplane
display RAM
display RAM
display RAM
display RAM
outputs (BP)
outputs (BP)
outputs (BP)
outputs (BP)
rows
rows
rows
rows
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
DP
DP
n
c
x
x
x
n
a
b
x
x
n
b
c
x
n
a
c
b
byte1
byte1
n + 1
n + 1
n + 1
n + 1
b
x
x
x
g
x
x
a
d
g
x
e
g
d
f
f
display RAM address/segment outputs (s)
display RAM address/segment outputs (s)
display RAM address/segment outputs (s)
display RAM address/segment outputs (s)
byte1
display RAM filling order
n + 2
n + 2
n + 2
a
e
e
byte2
x
x
x
c
x
x
f
x
x
n + 3
n + 3
DP
x
x
x
d
x
x
f
columns
columns
columns
columns
byte1
byte2
byte3
n + 4
g
x
x
x
n + 5
e
byte2
byte4
x
x
x
n + 6
byte3
d
x
x
x
byte5
n + 7
DP
x
x
x
2
C-bus
MSB
MSB
MSB
MSB
c b a f g e d DP
a b f g e c d DP
b DP c a d g f e
a c b DP f e g d
transmitted display byte
001aaj646
LSB
LSB
LSB
LSB