PCF2113DH/4,557 NXP Semiconductors, PCF2113DH/4,557 Datasheet
PCF2113DH/4,557
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PCF2113DH/4
PCF2113DH/4
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PCF2113DH/4,557 Summary of contents
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PCF2113x LCD controllers/drivers Rev. 04 — 4 March 2008 1. General description The PCF2113x is a low-power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2 lines of 12 characters or 1 line of ...
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... NXP Semiconductors I Multiplex rates (MUX) 1:18 (for normal operation), 1:9 (for single-line operation) and 1:2 (for Icon-only mode) I Uses common 11 code instruction set (extended) I Logic supply voltage range V battery cells LCD I Display supply voltage range V I Direct mode to save current consumption for Icon mode and MUX 1:9 (depending on ...
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... NXP Semiconductors 6. Block diagram BIAS V VOLTAGE LCDIN GENERATOR V LCDSENSE V LCD V LCDOUT GENERATOR V DD3 V DD1 V CHARACTER DD2 GENERATOR RAM (128 16 CHARACTERS V SS1 V SS2 DATA REGISTER (DR) 8 DB0 to DB3/SA0 DB4 to DB7 Fig 1. Block diagram of PCF2113x PCF2113_FAM_4 Product data sheet C1 to C60 60 COLUMN DRIVERS ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning V 1 DD1 OSC SS1 V 6 SS2 V 7 LCDOUT V 8 LCDIN R10 R11 11 R12 12 13 R13 14 R14 R15 15 R16 16 17 R18 C60 18 C59 19 C58 20 21 C57 C56 22 C55 23 24 C54 25 C53 Fig 2. Pin configuration for PCF2113DH (LQFP100) ...
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... NXP Semiconductors 84 dummy pad R17 96 SCL 97 SDA 100 R/W 101 DB7 102 DB6 103 DB5 104 DB4 105 DB3 106 DB2 107 DB1 108 DB0 V 109 DD2 V 110 DD3 111 dummy pad 7 Fig 3. Bonding pad locations for PCF2113xU (bottom view) Table 3 ...
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... NXP Semiconductors Table 3. Pin Table 4. Pad Type Bump dimensions Height difference in one die Convex deformation Pad size (aluminium) Passivation opening Pad pitch Wafer thickness (excluding bumps) Die size X Die size Y [1] Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9 (8 inch wafer). ...
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... NXP Semiconductors Table 5. Pin and bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Figure 3). Symbol Pin Type SS2 LCDOUT LCDSENSE LCDIN R10 10 O R11 11 O R12 12 O R13 13 O R14 ...
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... NXP Semiconductors Table 5. Pin and bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Figure 3). Symbol Pin Type C36 42 O C35 43 O C34 44 O C33 45 O C32 46 O C31 47 O C30 ...
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... NXP Semiconductors Table 5. Pin and bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Figure 3). Symbol Pin Type R17 86 O SCL 87 I SDA DB7 92 I/O DB6 93 I/O DB5 94 I/O ...
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... NXP Semiconductors 8. Functional description 8.1 LCD supply voltage generator The LCD supply voltage (V controlled by two internal 6-bit registers: VA and VB. program these registers. The nominal LCD operating voltage at room temperature is given by the relationship: V oper(nom) With a programmed value from 1 to 63, V Values producing more than 6 operating temperature are not allowed. Operation above this voltage may damage the device ...
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... NXP Semiconductors Table 6. Multiplex rate 1:18 1:9 1:2 [1] The values in the table are given relative to V 8.3 Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to V 8.4 External clock If an external clock used, this input is at the OSC pin ...
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... NXP Semiconductors 8.8 Address counter The Address Counter (AC) assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands ‘set DDRAM address’ and ‘set CGRAM address’. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter contents are output to the bus (DB6 to DB0) when bit and bit R ...
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... NXP Semiconductors Fig 6. Table 7. Mode Address space Read/write wrap-around (moves to next line) Display shift wrap-around (stays within line) 8.10 Character generator ROM The Character Generator ROM (CGROM) generates 240 character patterns format from 8-bit character codes. character sets that are currently implemented. ...
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... NXP Semiconductors upper 4 bits 0000 0001 0010 lower 4 bits xxxx 0000 1 2 xxxx 0001 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx ...
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... NXP Semiconductors upper 4 bits 0000 0001 0010 lower 4 bits xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The fi ...
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... NXP Semiconductors upper 4 bits 0000 0001 0010 lower 4 bits xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The fi ...
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... NXP Semiconductors upper 4 bits 0000 0001 0010 lower 4 bits xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 The fi ...
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... NXP Semiconductors 8.11 Character generator RAM user-defined characters may be stored in the Character Generator RAM (CGRAM). Some CGRAM characters (see icons (6 if icons blink and both icon rows are used in the application blink but both icon rows are used in the application icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the fi ...
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... NXP Semiconductors Fig 12. Cursor and blink display examples Fig 13. Example of a display with icons 8.13 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.14 LCD row and column drivers The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed ...
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... NXP Semiconductors V LCD ROW LCD ROW LCD ROW LCD COL LCD COL oper 0.5V oper 0.25V oper 0 V state 1 0.25V oper 0.5V oper V oper V oper 0.5V oper 0.25V oper 0 V state 2 0.25V oper 0.5V oper V oper R16 and R18 to be left open Fig 14. MUX 1:9 LCD waveforms ...
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... NXP Semiconductors V LCD ROW LCD ROW LCD ROW LCD COL LCD COL oper 0.5V oper 0.25V oper 0 V state 1 0.25V oper 0.5V oper V oper V oper 0.5V oper 0.25V oper 0 V state 2 0.25V oper 0.5V oper V oper Fig 15. MUX 1:18 LCD waveforms; Character mode ...
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... NXP Semiconductors V LCD ROW 17 2/3 1 LCD 2/3 ROW 18 1 LCD ROW 2/3 1 LCD 2/3 COL 1 ON/OFF 1 LCD 2/3 COL 2 OFF/ON 1 LCD 2/3 COL 3 ON/ON 1 LCD 2/3 COL 4 OFF/OFF 1 Fig 16. MUX 1:2 LCD waveforms; Icon mode (a) PCF2113_FAM_4 Product data sheet frame n frame n Rev. 04 — ...
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... NXP Semiconductors V oper 2/3V oper 1/3V oper state 1 COL 1 0 ROW 17 1/3V oper 2/3V oper V oper V oper 2/3V oper 1/3V state 2 oper COL 2 0 ROW 17 1/3V oper 2/3V oper V oper V oper 2/3V oper 1/3V oper state 3 COL 1 0 ROW 1/3V oper ...
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... NXP Semiconductors Table 8. Step Instructions Only two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR), can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ICs ...
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... NXP Semiconductors There are 4 types of instructions: • Designate PCF2113x functions such as display format, data length • Set internal RAM addresses • Perform data transfer with internal RAM • Other functions In normal use, data transfer instructions are used most frequently. However, automatic incrementing by 1 (or decrementing internal RAM addresses after each data write lessens the microcontroller program load ...
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... NXP Semiconductors Table 10. Instruction set with parallel bus commands Instruction Control and command bits RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry mode set Display control Cursor/display shift Set CGRAM address Set DDRAM address (extended functions) Reserved Screen configuration ...
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... NXP Semiconductors Table 11. Bit (no impact I S/C R/L L (no impact 9.1 Clear display ‘Clear display’ writes character code 20h into all DDRAM addresses (the character pattern for character code 20h must be a blank pattern), sets the DDRAM address counter to 0 and returns the display to its original position was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display ...
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... NXP Semiconductors 9.2 Return home ‘Return home’ sets the DDRAM address counter to 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change. ...
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... NXP Semiconductors 9.4.3 Bit B The character indicated by the cursor blinks when The cursor character blink is displayed by switching between display characters and all dots on with a period of approximately 1 s, with The cursor underline and the cursor character blink can be set to display simultaneously. 9.5 Cursor or display shift ‘ ...
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... NXP Semiconductors Remark: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (A6h to A0h). With the ‘set CGRAM address’ command, only bits DB5 to DB0 are set. Bit DB6 can be set using the ‘set DDRAM address’ command fi ...
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... NXP Semiconductors 10. Extended function set instructions and features 10.1 New instructions sets the chip into Extended instruction set mode. 10.2 Icon control The PCF2113x can drive up to 120 icons. See icon mapping. Fig 18. CGRAM to icon mapping (a) PCF2113_FAM_4 Product data sheet display: ...
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... NXP Semiconductors icon no. phase ROW/COL 1-5 even 17/1-5 6-10 even 17/6-10 11-15 even 17/11-15 56-60 even 17/56-60 61-65 even 18/1-5 116-120 even 18/56-60 1-5 odd (blink) 17/1-5 116-120 odd (blink) 18/56-60 CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. ...
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... NXP Semiconductors Icon states for the even phase are stored in CGRAM characters used (see Icon states for the odd phase are stored in CGRAM characters (another 120 bits for the 120 icons). When icon blink is disabled CGRAM characters may be used as normal CGRAM characters. ...
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... NXP Semiconductors 10.8 Display configuration 10.8.1 Bit P The P bit is used to flip the display left to right by mirroring the column data, as shown in Figure 20. This allows the display to be viewed from behind instead of front, enhances the flexibility in the assembly of equipment and avoids complicated data manipulation within the controller ...
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... NXP Semiconductors 10.9 Temperature control Default is bit TC1 = 0 and bit TC2 = 0. Selects the default temperature coefficient for the internally generated V Table 15. Bit TC1 10.10 Set V LCD The V LCD values for the Character mode and the Icon mode respectively. The generated V independent ...
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... NXP Semiconductors 11. Interfaces to microcontroller 11.1 Parallel interface The PCF2113x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/W are required (see In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for the transaction ...
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... NXP Semiconductors RS R/W E internal DB7 IR7 instruction IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit. Fig 23. Example of 4-bit data transfer timing sequence RS R/W E internal data DB7 instruction write Fig 24. Example of busy flag checking timing sequence 2 11 ...
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... NXP Semiconductors Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration) ...
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... NXP Semiconductors acknowledgement slave address R (1) Last data byte is a dummy byte (may be omitted). Fig 26. Master reads after setting word address; write word address; set RS; ‘read data’ SLAVE S ADDRESS Fig 27. Master reads slave immediately after first byte; read mode (RS previously defined) ...
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... NXP Semiconductors Fig 29. Bit transfer SDA SCL Fig 30. Definition of START and STOP conditions by transmitter Fig 31. Acknowledgement on the I 11.2.2 Definitions • Transmitter: the device that sends the data to the bus • Receiver: the device that receives the data from the bus • ...
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... NXP Semiconductors 12. Internal circuitry Table 17. Symbol V DD1 V DD2 V DD3 V SS1 V SS2 V LCDSENSE V LCDIN V LCDOUT SCL SDA PCF2113_FAM_4 Product data sheet Device protection circuits Pad Internal circuit 1 109 110 Rev. 04 — 4 March 2008 PCF2113x LCD controllers/drivers V DD1 V SS1 mgu200 V SS1 V DD3 V SS1 ...
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... NXP Semiconductors Table 17. Symbol OSC R/W DB0 to DB7 R16 R17 R18 C27 C28 to C52 C53 to C60 13. Limiting values Table 18. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DD1 V DD2 V DD3 V LCD V i( DD(LCD) P tot P/out V esd I lu ...
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... NXP Semiconductors [1] HBM: Human Body Model, according to JESD22-A114. [2] MM: Machine Model, according to JESD22-A115. [3] CDM: Charged-Device Model, according to JESD22-C101. [4] Latch-up testing, according to JESD78. 14. Static characteristics Table 19. Static characteristics DD1 DD2 DD3 unless otherwise specified. Symbol Parameter Supplies V supply voltage 1 DD1 ...
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... NXP Semiconductors Table 19. Static characteristics DD1 DD2 DD3 unless otherwise specified. Symbol Parameter Pins DB7 to DB0 I LOW-level output OL current I HIGH-level output OH current I pull-up current C-bus Input on pins SDA and SCL V input voltage I V LOW-level input voltage IL V HIGH-level input ...
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... NXP Semiconductors 15. Dynamic characteristics Table 20. Dynamic characteristics DD1 DD2 DD3 unless otherwise specified Symbol Parameter f LCD frame frequency fr(LCD) f oscillator frequency osc f external oscillator frequency osc(ext) t start-up delay time on pin OSC d(startup)(OSC) t power-down pulse width w(pd) t spike pulse width ...
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... NXP Semiconductors Table 20. Dynamic characteristics DD1 DD2 DD3 unless otherwise specified Symbol Parameter t set-up time for STOP condition SU;STO t pulse width of spikes that must SP be suppressed by the input filter t bus free time between a STOP BUF and START condition [1] Not available at any pin. ...
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... NXP Semiconductors SDA SCL SDA Fig 34. I 16. Application information 16.1 Application diagrams Fig 35. Direct connection to 8-bit microcontroller; 4-bit bus Fig 36. Direct connection to 8-bit microcontroller; 8-bit bus PCF2113_FAM_4 Product data sheet t t BUF LOW t HD;STA C-bus timing diagram P10 RS P11 R/W P12 ...
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... NXP Semiconductors Fig 37. Typical application using parallel interface V SCL SDA Fig 38. Application using I PCF2113_FAM_4 Product data sheet OSC PCF2113x 470 V LCD nF 100 DB7 to DB0 OSC PCF2113x 470 V LCD nF 100 OSC PCF2113x 470 V LCD nF 100 MASTER TRANSMITTER PCF84C81A; P80CL410 2 C-bus interface Rev. 04 — ...
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... NXP Semiconductors 16.2 General application information The required minimum value for the external capacitors in an application with the PCF2113x are Higher capacitor values are recommended for ripple reduction. SS For COG applications the recommended Indium Tin Oxide (ITO) track resistance minimized for the I/O and supply connections. Optimized values for these tracks are below ...
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... NXP Semiconductors when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the ‘return home’ operation is performed. Table 22. 8-bit operation, 1-line display example; using internal reset (character set ‘A’) ...
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... NXP Semiconductors Table 22. 8-bit operation, 1-line display example; using internal reset (character set ‘A’) Step Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 25 cursor/display shift ‘write data’ to CGRAM/DDRAM return home Table 23. 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’) ...
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... NXP Semiconductors Table 23. 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’) Step Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 15 ‘write data’ to CGRAM/DDRAM ‘write data’ to CGRAM/DDRAM return home 16.5 8-bit operation, 2-line display For a 2-line display the cursor automatically moves from the fi ...
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... NXP Semiconductors Table 24. 8-bit operation, 2-line display example; using internal reset Step Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 13 ‘write data’ to CGRAM/DDRAM ‘write data’ to CGRAM/DDRAM entry mode set ‘write data’ to CGRAM/DDRAM return home 16.6 I C-bus operation, 1-line display ...
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... NXP Semiconductors 2 Table 25. Example of I C-bus operation; 1-line display (using internal reset, assuming SA0 = V 2 Step I C-bus byte C-bus start 8 slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack send a control byte for ‘write data’ ‘write data’ to DDRAM ...
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... NXP Semiconductors 2 Table 25. Example of I C-bus operation; 1-line display (using internal reset, assuming SA0 = V 2 Step I C-bus byte 23 ‘read data’: 8 SCL + master acknowledge DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack ‘read data’: 8 SCL + master acknowledge DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack ...
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... NXP Semiconductors Table 26. Initialization by instruction, 8-bit interface Step Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 initialization ends [ not relevant. Table 27. Initialization by instruction, 4-bit interface; not applicable for I Step Instruction 1 internal reset 2 wait R/W DB7 wait R/W DB7 wait more than 40 s ...
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... NXP Semiconductors 17. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 18. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5 . 19. Packing information Fig 40. Tray details Table 28. Symbol PCF2113_FAM_4 Product data sheet ...
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... NXP Semiconductors Fig 41. Tray alignment The orientation of the pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram on the die surface. 20. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • ...
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... NXP Semiconductors Table 30. Package thickness (mm) < 1.6 1.6 to 2.5 > 2.5 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Fig 42. Temperature profiles for large and small components For further information on temperature profi ...
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... Document ID Release date PCF2113_FAM_4 20080304 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Figure • Table 2 • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . 10 8.1 LCD supply voltage generator . . . . . . . . . . . . 10 8.2 LCD bias voltage generator . . . . . . . . . . . . . . 10 8.3 Oscillator 8.4 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.5 Power-on reset ...
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... NXP Semiconductors 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 62 22 Legal information 22.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 63 22.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 22.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 22.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 23 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 LCD controllers/drivers Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. ...