MAX6951CEE+T Maxim Integrated Products, MAX6951CEE+T Datasheet - Page 6
![IC DRVR DSPL LED SRL 16-QSOP](/photos/7/35/73543/16-qsop_21-0112_sml.jpg)
MAX6951CEE+T
Manufacturer Part Number
MAX6951CEE+T
Description
IC DRVR DSPL LED SRL 16-QSOP
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX6950CEE.pdf
(19 pages)
Specifications of MAX6951CEE+T
Display Type
LED
Configuration
7 Segment
Interface
3-Wire Serial
Digits Or Characters
8 Digits
Current - Supply
10mA
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-QSOP Exposed Pad, 16-eQSOP , 16-HQSOP
Number Of Digits
8
Number Of Segments
64
Low Level Output Current
400 mA
High Level Output Current
- 50 mA
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Supply Current
15 mA
Maximum Power Dissipation
667 mW
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The serial interface comprises a 16-bit shift register into
which DIN data is clocked on the rising edge of CLK
when CS is low. When CS is high, transitions on CLK do
not clock data into the shift register. When CS goes
high, the 16 bits in the shift register are parallel loaded
into a 16-bit latch. The 16 bits in the latch are then
decoded to determine and execute the command.
The MAX6950/MAX6951 are written to using the follow-
ing sequence (Figure 2):
1) Take CLK low.
2) Take CS low. This enables the internal 16-bit shift
3) Clock 16 bits of data in order, D15 first to D0 last,
4) Take CS high.
CLK and DIN may well be used to transmit data to other
peripherals. The MAX6950/MAX6951 ignore all activity
on CLK and DIN except when CS is low. Data cannot
be read from the MAX6950/MAX6951.
If fewer or greater than 16 bits are clocked into the
MAX6950/MAX6951 between taking CS low and taking
CS high again, the MAX6950/MAX6951 store the last 16
bits received, including the previous transmission(s).
The general case is when n bits (where n > 16) are
transmitted to the MAX6950/MAX6951. The last bits
comprising bits {n-15} to {n} are retained and are paral-
lel loaded into the 16-bit latch as bits D15 to D0,
respectively (Figure 3).
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 1. Standard Driver Connection to Single-Digit Displays
Table 2. Serial-Data Format (16 Bits)
6
LED Digit 0
LED Digit 1
LED Digit 2
LED Digit 3
LED Digit 4
LED Digit 5
LED Digit 6
LED Digit 7
D15
register.
into DIN, observing the setup and hold times.
_______________________________________________________________________________________
D14
DIG/SEG0
SEG dp
SEG dp
SEG dp
SEG dp
SEG dp
SEG dp
SEG dp
D13
PIN 6
CC0
D12
ADDRESS
DIG/SEG1
SEG dp
SEG g
SEG g
SEG g
SEG g
SEG g
SEG g
PIN 5
CC1
D11
DIG/SEG2
D10
SEG g
SEG g
PIN 4
SEG f
SEG f
SEG f
SEG f
SEG f
CC2
D9
DIG/SEG3
SEG e
SEG e
SEG e
SEG e
PIN 3
SEG f
SEG f
SEG f
CC3
D8
MSB
DIG/SEG4
Table 3 lists the addressable Digit and Configuration
registers. The digit registers are implemented by two
planes of 8-byte dual-port SRAM, P0 and P1.
On initial power-up, all control registers are reset, the
display is blanked, and the MAX6950/MAX6951 enter
shutdown mode. Program the display driver prior to dis-
play use. Otherwise, it is initially set to scan five digits, it
does not decode data in the data registers, and the
Intensity register is set to its minimum value. Table 4
lists the register status after power-up.
The configuration register is used to enter and exit shut-
down, select the blink rate, globally enable and disable
the blink function, globally clear the digit data, and
reset the blink timing. Bit position D1 should always be
written with a zero when the configuration register is
updated. See Table 5 for configuration register format.
The S bit selects shutdown or normal operation.
The B bit selects the blink rate.
The E bit globally enables or disables the blink function.
The T bit resets the blink timing.
The R bit globally clears the digit data for both planes
P0 and P1 for all digits.
When the MAX6950/MAX6951 are in shutdown mode
(Table 6), the scan oscillator is halted; all segment and
digit drivers are high impedance. Data in the digit and
D7
PIN 14
SEG d
SEG d
SEG d
SEG e
SEG e
SEG e
SEG e
CC4
D6
DIG/SEG5
PIN 13
SEG d
SEG d
SEG d
SEG d
SEG d
SEG c
SEG c
CC5
D5
Digit and Control Registers
D4
DIG/SEG6
DATA
PIN 12
SEG c
SEG c
SEG c
SEG c
SEG c
SEG c
SEG b
CC6
Configuration Register
D3
DIG/SEG7
Initial Power-Up
PIN 11
SEG b
SEG b
SEG b
SEG b
SEG b
SEG b
SEG b
D2
CC7
D1
PIN 10
SEG 8
SEG a
SEG a
SEG a
SEG a
SEG a
SEG a
SEG a
SEG a
LSB
D0