ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet
ADE7878ACPZ
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ADE7878ACPZ Summary of contents
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FEATURES Highly accurate; supports EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards Compatible with 3-phase 4-wire (delta or wye), and other 3-phase services Supplies total (fundamental and harmonic) active, reactive (ADE7878, ADE7868, and ADE7858 ...
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ADE7854/ADE7858/ADE7868/ADE7878 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagrams............................................................. 4 Specifications..................................................................................... 8 Timing Characteristics .............................................................. 11 Absolute Maximum Ratings.......................................................... 14 Thermal Resistance .................................................................... 14 ESD Caution................................................................................ 14 Pin Configuration ...
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B to Rev. C Change to Signal-to-Noise-and-Distortion Ratio, SINAD Parameter, Table 1 .............................................................................9 Changes to Figure 18 ......................................................................18 Changes to Figure 22 ......................................................................19 Changes to Silicon Anomaly Section............................................72 Added Table 28 to Silicon Anomaly Section, Renumbered Tables Sequentially ..........................................................................73 ...
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ADE7854/ADE7858/ADE7868/ADE7878 FUNCTIONAL BLOCK DIAGRAMS Figure 1. ADE7854 Functional Block Diagram Rev Page 08510-204 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Figure 2. ADE7858 Functional Block Diagram Rev Page 08510-203 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Figure 3. ADE7868 Functional Block Diagram Rev Page 0- ...
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ADE7854/ADE7858/ADE7868/ADE7878 Figure 4. ADE7878 Functional Block Diagram Rev Page 0 ...
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ADE7854/ADE7858/ADE7868/ADE7878 SPECIFICATIONS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T Table 2. Parameter 1, 2 ACCURACY Active Energy Measurement Active Energy Measurement Error (per Phase) Total Active Power Fundamental ...
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Parameter DC Power Supply Rejection Output Frequency Variation Total Reactive Energy Measurement Bandwidth RMS MEASUREMENTS I rms and V rms Measurement Bandwidth I rms and V rms Measurement Error (PSM0 Mode) MEAN ABSOLUTE VALUE (MAV) MEASUREMENT (ADE7868 AND ...
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ADE7854/ADE7858/ADE7868/ADE7878 1, 2 Parameter CLKIN Input Clock Frequency Crystal Equivalent Series Resistance CLKIN Input Capacitance CLKOUT Output Capacitance LOGIC INPUTS—MOSI/SDA, SCLK/SCL, SS, RESET, PM0, AND PM1 Input High Voltage, V INH Input Low Voltage, V INL Input Current ...
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TIMING CHARACTERISTICS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T function pin names are referenced by the relevant function only within the timing tables and diagrams; see the Pin ...
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ADE7854/ADE7858/ADE7868/ADE7878 Table 4. SPI Interface Timing Parameters Parameter SS to SCLK Edge SCLK Period SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After SCLK Edge Data Input Setup Time Before SCLK Edge Data Input Hold Time After ...
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Table 5. HSDC Interface Timing Parameter Parameter HSA to HSCLK Edge HSCLK Period HSCLK Low Pulse Width HSCLK High Pulse Width Data Output Valid After HSCLK Edge Data Output Fall Time Data Output Rise Time HSCLK Rise Time HSCLK Fall ...
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ADE7854/ADE7858/ADE7868/ADE7878 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 6. Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND, IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP, VCP, VN Analog Input Voltage to INP ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic 1, 10, 11, 20, NC 21, 30, 31 PM0 3 PM1 4 RESET 5 DVDD 6 DGND 7, 8 IAP, IAN 9, 12 IBP, IBN ...
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ADE7854/ADE7858/ADE7868/ADE7878 Pin No. Mnemonic 18, 19, 22, 23 VN, VCP, VBP, VAP 24 AVDD 25 AGND 26 VDD 27 CLKIN 28 CLKOUT 29, 32 IRQ0, IRQ1 33, 34, 35 CF1, CF2, CF3/HSCLK 36 SCLK/SCL 37 MISO/HSD 38 MOSI/SDA 39 SS/HSA ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.05 0 –0.05 +85°C, POWER FACTOR = 1.0 –0.10 +25°C, POWER FACTOR = 1.0 –40°C, POWER FACTOR = 1.0 –0.15 –0.20 –0.25 –0.30 –0.35 –0.40 0.01 0.1 1 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 10. Total ...
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ADE7854/ADE7858/ADE7868/ADE7878 0.30 0.20 0.10 0 –0.10 –0.20 –0.30 0.01 0.1 1 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 16. Total Reactive Energy Error As Percentage of Reading (Gain = +1, Power Factor = 0) over Power Supply with Internal Reference and ...
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TEST CIRCUIT 10kΩ 1kΩ 18nF 18nF 1kΩ 1kΩ 18nF 18nF 1kΩ ADE7854/ADE7858/ADE7868/ADE7878 3. 0.22µF 4.7µF 4.7µ 3.3V PM0 2 SS/HSA 39 PM1 3 1µF MOSI/SDA 38 RESET 4 MISO/HSD 37 IAP 7 SCLK/SCL 36 IAN ...
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ADE7854/ADE7858/ADE7868/ADE7878 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7854/ADE7858/ADE7868/ADE7878 is defined by Measurement Error = − Energy Registered by ADE 7878 True True Energy Phase Error Between Channels The high-pass filter (HPF) and digital ...
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POWER MANAGEMENT The ADE7868/ADE7878 have four modes of operation, deter- mined by the state of the PM0 and PM1 pins (see Table 9). The ADE7854/ADE7858 have two modes of operation. These pins provide complete control of the ADE7854/ADE7858/ADE7868/ ADE7878 operation ...
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ADE7854/ADE7858/ADE7868/ADE7878 LPLINE[4: and LPOIL[2: The test period is three 50 Hz cycles (60 ms), and the Phase A current rises above the LPOIL[2:0] threshold three times. At the end of the test period, the IRQ1 pin ...
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Table 12. Recommended Actions When Changing Power Modes Recommended Actions Initial Power Before Setting Next Mode Power Mode PSM0 Stop DSP by setting the run register = 0x0000. Disable HSDC by clearing Bit 6 (HSDEN the CONFIG ...
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ADE7854/ADE7858/ADE7868/ADE7878 POWER-UP PROCEDURE 3.3V – 10% 2.0V ± 10% 0V ADE78xx POWERED UP The ADE7854/ADE7858/ADE7868/ADE7878 contain an on- chip power supply monitor that supervises the power supply (VDD). At power-up, until VDD reaches 2 V ± 10%, the chip is ...
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CONFIG2 and LPOILVL registers. The ADE78xx signals the end of the transition period by triggering the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in the STATUS1 register to 1. This bit is 0 during ...
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ADE7854/ADE7858/ADE7868/ADE7878 THEORY OF OPERATION ANALOG INPUTS The ADE7868/ADE7878 have seven analog inputs forming current and voltage channels. The ADE7854/ADE7858 have six analog inputs, not offering the neutral current. The current channels consist of four pairs of fully differential voltage inputs: ...
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kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization ...
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ADE7854/ADE7858/ADE7868/ADE7878 PGA1 BITS REFERENCE GAIN[2:0] ×1, ×2, ×4, ×8, ×16 IAP V PGA1 ADC IN IAN V IN +0.5V/GAIN 0V 0xA58AC0 = –0.5V/GAIN ANALOG INPUT RANGE PGA2 BITS GAIN[5:3] ×1, ×2, ×4, ×8, ×16 INP V PGA2 IN INN Current ...
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Current Channel Sampling The waveform samples of the current channel are taken at the output of HPF and stored in the 24-bit signed registers, IAWV, IBWV, ICWV, and INWV (ADE7868 and ADE7878 only rate of 8 kSPS. All ...
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ADE7854/ADE7858/ADE7868/ADE7878 –15 –20 –25 – FREQUENCY (Hz) –89.96 –89.97 –89.98 –89. FREQUENCY (Hz) Figure 38. Combined Gain and Phase Response of the Digital Integrator ( Hz) As ...
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Voltage Waveform Gain Registers There is a multiplier in the signal path of each phase voltage. The voltage waveform can be changed by ±100% by writing a corresponding twos complement number to the 24-bit signed current waveform gain registers (AVGAIN, ...
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ADE7854/ADE7858/ADE7868/ADE7878 POWER QUALITY MEASUREMENTS Zero-Crossing Detection The ADE7854/ADE7858/ADE7868/ADE7878 have a zero- crossing (ZX) detection circuit on the phase current and voltage channels. The neutral current datapath does not contain a zero- crossing detection circuit. Zero-crossing events are used as a ...
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The regular succession of these zero-crossing events is Phase A followed by Phase B followed by Phase C (see Figure 44). If the sequence of zero-crossing events is, instead, Phase A followed by Phase C ...
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ADE7854/ADE7858/ADE7868/ADE7878 PHASE A PHASE B ANGLE2 ANGLE1 ANGLE0 Figure 46. Delays Between Phase Voltages (Currents) The ANGLE0, ANGLE1, and ANGLE2 registers are 16-bit unsigned registers with 1 LSB corresponding to 3.90625 μs (256 kHz clock), which means a resolution of ...
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MASK1 is set, the IRQ1 interrupt pin is driven low in case of a SAG event in the same moment the Status Bit 16 (SAG) in STATUS1 register is set to 1. The SAG status bit in the STATUS1 register ...
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ADE7854/ADE7858/ADE7868/ADE7878 Figure 49 shows how the ADE78xx records the peak value on the current channel when measurements on Phase A and Phase B are enabled (Bit PEAKSEL[2:0] in the MMODE register are 011). PEAKCYC is set to 16, meaning that ...
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Overvoltage and Overcurrent Level Set The content of the overvoltage (OVLVL), and overcurrent, (OILVL) 24-bit unsigned registers is compared to the absolute value of the voltage and current channels. The maximum value of these registers is the maximum value of ...
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ADE7854/ADE7858/ADE7868/ADE7878 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for the small phase errors. The phase calibration registers (APHCAL, BPHCAL, and CPHCAL) are 10-bit registers that can vary the time ...
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REFERENCE CIRCUIT The nominal reference voltage at the REF 0.075% V. This is the reference voltage used for the ADCs in the ADE7854/ADE7858/ADE7868/ADE7878. The REF pin can be overdriven by an external source, for example, an external 1.2 V reference. ...
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ADE7854/ADE7858/ADE7868/ADE7878 • If the ADE7854/ADE7858/ADE7868/ADE7878 registers located in the data memory RAM have not been modified, write 0x0001 into the run register to start the DSP. • If the ADE7854/ADE7858/ADE7868/ADE7878 registers located in the data memory RAM have to be ...
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Table 13. Settling Time for I rms Measurement Integrator Status 50 Hz Input signals Integrator Off 440 ms Integrator On 550 ms CURRENT SIGNAL FROM HPF OR INTEGRATOR ADE7854/ADE7858/ADE7868/ADE7878 As stated in the Current Waveform Gain Registers section, the serial ...
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ADE7854/ADE7858/ADE7868/ADE7878 Current RMS Offset Compensation The ADE7854/ADE7858/ADE7868/ADE7878 incorporate a current rms offset compensation register for each phase: AIRMSOS, BIRMSOS, CIRMSOS registers, and the NIRMSOS register for ADE7878 and ADE7868 only. These are 24-bit signed registers that are used to remove ...
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The voltage rms values are signed 24-bit values and they are stored into the Registers AVRMS, BVRMS, and CVRMS. The update rate of the current rms measurement is 8 kHz. With the specified full-scale analog input signal ...
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ADE7854/ADE7858/ADE7868/ADE7878 Voltage RMS Offset Compensation The ADE78xx incorporates voltage rms offset compensation registers for each phase: AVRMSOS, BVRMSOS, and CVRMSOS. These are 24-bit signed registers used to remove offsets in the voltage rms calculations. An offset can exist in the ...
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If the phase currents and voltages contain only the fundamental component, are in phase (that is φ = γ full-scale ADC inputs, then multiplying them results in an instantaneous power signal that has a dc component, V ...
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ADE7854/ADE7858/ADE7868/ADE7878 The output is scaled by −50% by writing 0xC00000 to the watt gain registers, and it is increased by +50% by writing 0x400000 to them. These registers are used to calibrate the active power (or energy) calculation in the ...
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HPFDIS [23:0] AIGAIN IA HPF HPFDIS [23:0] APHCAL AVGAIN VA HPF DIGITAL SIGNAL PROCESSOR The ADE7854/ADE7858/ADE7868/ADE7878 achieve the integration of the active power signal in two stages (see Figure 62). The process is identical for both total and fundamental active ...
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ADE7854/ADE7858/ADE7868/ADE7878 CFWATTHR 32-bit signed registers. The active energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the active power is positive. Conversely, if the active power is negative, the energy register underflows to ...
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ZXSEL[0] IN LCYCMODE[7:0] ZERO- CROSSING DETECTION (PHASE A) ZXSEL[1] IN LCYCMODE[7:0] ZERO- CROSSING DETECTION (PHASE B) ZXSEL[2] IN LCYCMODE[7:0] ZERO- CROSSING DETECTION (PHASE C) AWATTOS AWGAIN OUTPUT FROM LPF2 ACCUMULATOR WTHR[47:0] Figure 65. Line Cycle Active Energy Accumulation Mode The ...
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ADE7854/ADE7858/ADE7868/ADE7878 The average total reactive power over an integral number of line cycles (n) is given by the expression in Equation 33. ∞ ∑ = ∫ cos(φ – γ ...
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The ADE7858/ADE7868/ADE7878 have sign detection circuitry for reactive power calculations that can monitor the total reactive powers or the fundamental reactive powers. As described in the Reactive Energy Calculation section, the reactive energy accu- mulation is executed in two stages. ...
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ADE7854/ADE7858/ADE7868/ADE7878 ⎧ ∫ = ⎨ ReactiveEn ergy Lim ⎩ → where the discrete time sample number the sample period. On the ADE7858/ADE7868/ADE7878, the total phase reactive powers ...
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Integration Time Under A Steady Load The discrete time sample period (T) for the accumulation register is 125 μs (8 kHz frequency). With full-scale pure sinusoidal signals on the analog inputs and a 90° phase difference between the vol- tage ...
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ADE7854/ADE7858/ADE7868/ADE7878 APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. One way to obtain the apparent power is by multiplying the voltage rms value by the current rms value (also called ...
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Apparent Power Gain Calibration The average apparent power result in each phase can be scaled by ±100% by writing to one of the phase’s VAGAIN 24-bit registers (AVAGAIN, BVAGAIN, or CVAG AIN). The VAGAIN registers are twos complement, signed registers ...
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ADE7854/ADE7858/ADE7868/ADE7878 In the ADE7854/ADE7858/ADE7868/ADE7878, the phase apparent powers are accumulated in the AVAHR, BVAHR, and CVAHR 32-bit signed registers. The apparent energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the apparent power ...
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The line cycle apparent energy accumulation mode is activated by setting Bit 2 (LVA) in the LCYCMODE register. The apparent energy accumulated over an integer number of zero crossings is written to the xVAHR accumulation registers after the number of ...
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ADE7854/ADE7858/ADE7868/ADE7878 Second, Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and Bits[8:6] (CF3SEL[2:0]) in the CFMODE register decide what type of power is used at the inputs of the CF1, CF2, and CF3 converters, respectively. Table 22 shows the values that CFxSEL can have: ...
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By default, the TERMSELx bits are all 1 and the CF1SEL bits are 000, the CF2SEL bits are 001, and the CF3SEL bits are 010. This means that by default, the CF1 digital-to-frequency converter produces signals proportional to the sum ...
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ADE7854/ADE7858/ADE7868/ADE7878 Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the CFMODE register enable this process when set to 1. When cleared to 0, the default state, no latch occurs. The process is available even if the CFx output is not enabled by ...
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REACTIVE ENERGY NO-LOAD THRESHOLD REACTIVE POWER NO-LOAD THRESHOLD NO-LOAD THRESHOLD ACTIVE POWER REVRPx BIT IN STATUS0 xVARSIGN BIT IN PHSIGN POS VARNOLOAD SIGN = POSITIVE Figure 76. Reactive Power Accumulation in Sign Adjusted Mode Sign of Sum-of-Phase Powers in the ...
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ADE7854/ADE7858/ADE7868/ADE7878 Bit 0 (NLOAD) in the STATUS1 register is set when this no load condition in one of the three phases is triggered. Bits[2:0] (NLPHASE[2:0]) in the PHNOLOAD register indicate the state of all phases relative load ...
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CHECKSUM REGISTER The ADE7854/ADE7858/ADE7868/ADE7878 have a checksum 32-bit register, CHECKSUM, that ensures certain very important configuration registers maintain their desired value during Normal Power Mode PSM0. The registers covered by this register are MASK0, MASK1, COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, ...
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ADE7854/ADE7858/ADE7868/ADE7878 INTERRUPTS The ADE7854/ADE7858/ADE7868/ADE7878 have two interrupt pins, IRQ0 and IRQ1 . Each of the pins is managed by a 32-bit interrupt mask register, MASK0 and MASK1, respectively. To enable an interrupt, a bit in the MASKx register must be ...
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IRQx GLOBAL CLEAR MCU PROGRAM JUMP INTERRUPT INTERRUPT TO ISR SEQUENCE MASK FLAG t 1 IRQx GLOBAL PROGRAM JUMP INTERRUPT TO ISR SEQUENCE MASK Figure 80. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved status ...
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ADE7854/ADE7858/ADE7868/ADE7878 Write Operation 2 The write operation using the I C interface of the ADE7854/ ADE7858/ADE7868/ADE7878 initiate when the master generates a start condition and consists in one byte representing the address of the ADE78xx followed by ...
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I C Read Operation 2 The read operation using the I C interface of the ADE7854/ ADE7858/ADE7868/ADE7878 is accomplished in two stages. The first stage sets the pointer to the address of the register. The second stage reads the ...
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ADE7854/ADE7858/ADE7868/ADE7878 SPI-Compatible Interface The SPI of the ADE7854/ADE7858/ADE7868/ADE7878 is always a slave of the communication and consists of four pins (with dual functions): SCLK/SCL, MOSI/SDA, MISO/HSD, and SS /HSA. The functions used in the SPI-compatible interface are SCLK, MOSI, MISO, ...
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SPI Write Operation The write operation using the SPI interface of the ADE78xx initiates when the master sets the SS /HSA pin low and begins sending one byte representing the address of the ADE7854/ ADE7858/ADE7868/ADE7878 on the MOSI line. The ...
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ADE7854/ADE7858/ADE7868/ADE7878 HSDC Interface The high speed data capture (HSDC) interface is disabled after default. It can be used only if the ADE7854/ADE7858/ADE7868/ 2 ADE7878 is configured with interface. The SPI interface of the ADE7854/ADE7858/ADE7868/ADE7878 cannot be used ...
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Figure 89 shows the HSDC transfer protocol for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the HSDC interface introduces a seven-HSCLK cycles gap between every 8-bit word. See Table 53 for the ...
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ADE7854/ADE7858/ADE7868/ADE7878 HSCLK 31 24 HSDATA IAVW (BYTE 3) HSACTIVE Figure 89. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0 ADE7878 EVALUATION BOARD An evaluation board built upon the ADE7878 configuration supports all ...
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... ADE7878ACPZ Version = 4 ADE7854ACPZ ADE7858ACPZ ADE7868ACPZ ADE7878ACPZ FUNCTIONALITY ISSUES Table 25. Offset RMS Registers Cannot be Set to Negative Values [er001, Version = 2 Silicon] Background When the AIRMSOS, AVRMSOS, BIRMSOS, BVRMSOS, CIRMSOS, CVRMSOS, and NIRMSOS registers are set to a negative value, for sufficiently small inputs, the argument of the square root used in the rms data path may become negative. In this case, the corresponding AIRMS, AVRMS, BIRMS, BVRMS, CIRMS, or CVRMS rms register is automatically set to 0 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Table 27. The Read-Only RMS Registers May Show the Wrong Value [er003, Version = 2 Silicon] Background The read-only rms registers (AVRMS, BVRMS, CVRMS, AIRMS, BIRMS, CIRMS, and NIRMS) can be read without restrictions at any time. Issue The ...
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REGISTERS LIST Table 30. Registers List Located in DSP Data Memory RAM Register Bit 1 Address Name R/W Length 0x4380 AIGAIN R/W 24 0x4381 AVGAIN R/W 24 0x4382 BIGAIN R/W 24 0x4383 BVGAIN R/W 24 0x4384 CIGAIN R/W 24 0x4385 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Register Bit 1 Address Name R/W Length 0x43A3 AFVARGAIN R/W 24 0x43A4 AFVAROS R/W 24 0x43A5 BFVARGAIN R/W 24 0x43A6 BFVAROS R/W 24 0x43A7 CFVARGAIN, R/W 24 0x43A8 CFVAROS R/W 24 0x43A9 VATHR1 R/W 24 0x43AA VATHR0 R/W 24 ...
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Register Bit 1 Address Name R/W Length 4 0x43B9 to Reserved N/A N/A 0x43BE 0x43BF ISUM R 28 0x43C0 AIRMS R 24 0x43C1 AVRMS R 24 0x43C2 BIRMS R 24 0x43C3 BVRMS R 24 0x43C4 CIRMS R 24 0x43C5 CVRMS ...
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ADE7854/ADE7858/ADE7868/ADE7878 Register Bit 1, 2 Address Name R/W Length 0xE40C AVAHR R 32 0xE40D BVAHR R 32 0xE40E CVAHR read, and W is write. 2 N/A is not applicable unsigned register, and ...
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Register Bit 1 Address Name R/W Length 0xE519 AVA R 24 0xE51A BVA R 24 0xE51B CVA R 24 0xE51F CHECKSUM R 32 0xE520 VNOM R/W 24 0xE521 to Reserved 0xE52E 0xE600 PHSTATUS R 16 0xE601 ANGLE0 R 16 0xE602 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Register Bit 1 Address Name R/W Length 0xE707 Version R/W 8 0xEBFF Reserved 8 0xEC00 LPOILVL R/W 8 0xEC01 CONFIG2 R read, and W is write 24- or 20-bit signed or ...
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Bit Location Bit Mnemonic Default Value 6 REVAPA 0 7 REVAPB 0 8 REVAPC 0 9 REVPSUM1 0 10 REVRPA 0 11 REVRPB 0 12 REVRPC 0 13 REVPSUM2 0 14 CF1 15 CF2 16 CF3 17 DREADY 0 18 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Bit Location Bit Mnemonic Default Value 2 VANLOAD 0 3 ZXTOVA 0 4 ZXTOVB 0 5 ZXTOVC 0 6 ZXTOIA 0 7 ZXTOIB 0 8 ZXTOIC 0 9 ZXVA 0 10 ZXVB 0 11 ZXVC 0 12 ZXIA 0 ...
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Bit Location Bit Mnemonic Default Value 4 VAEHF 0 5 LENERGY 0 6 REVAPA 0 7 REVAPB 0 8 REVAPC 0 9 REVPSUM1 0 10 REVRPA 0 11 REVRPB 0 12 REVRPC 0 13 REVPSUM2 0 14 CF1 15 CF2 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Bit Location Bit Mnemonic Default Value 5 ZXTOVC 0 6 ZXTOIA 0 7 ZXTOIB 0 8 ZXTOIC 0 9 ZXVA 0 10 ZXVB 0 11 ZXVC 0 12 ZXIA 0 13 ZXIB 0 14 ZXIC 0 15 RSTDONE 0 ...
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Bit Location Bit Mnemonic Default Value 14 VSPHASE[ Reserved 0 Table 42. PHNOLOAD Register (Address 0xE608) Bit Location Bit Mnemonic Default Value 0 NLPHASE[ NLPHASE[ NLPHASE[ FNLPHASE[ FNLPHASE[ ...
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ADE7854/ADE7858/ADE7868/ADE7878 Bit Location Bit Mnemonic Default Value 8 TERMSEL3[2] 1 10:9 ANGLESEL[1: VNOMAEN 0 12 VNOMBEN 0 13 VNOMCEN 0 14 SELFREQ 0 15 Reserved 0 Table 44. Gain Register (Address 0xE60F) Bit Location Bit Mnemonic Default Value ...
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Table 45. CFMODE Register (Address 0xE610) Bit Location Bit Mnemonic Default Value 2:0 CF1SEL[2:0] 000 5:3 CF2SEL[2:0] 001 8:6 CF3SEL[2:0] 010 9 CF1DIS 1 10 CF2DIS 1 11 CF3DIS 1 ADE7854/ADE7858/ADE7868/ADE7878 Description 000: the CF1 frequency is proportional to the ...
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ADE7854/ADE7858/ADE7868/ADE7878 Bit Location Bit Mnemonic Default Value 12 CF1LATCH 0 13 CF2LATCH 0 14 CF3LATCH 0 15 Reserved 0 Table 46. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616) Bit Location Bit Mnemonic Default Value 9:0 PHCALVAL 0000000000 ...
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Bit Location Bit Mnemonic Default Value 8 SUM3SIGN 0 15:9 Reserved 000 0000 Table 48. CONFIG Register (Address 0xE618) Bit Location Bit Mnemonic Default Value 0 INTEN 0 2:1 Reserved 00 3 SWAP 0 4 MOD1SHORT 0 5 MOD2SHORT 0 ...
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ADE7854/ADE7858/ADE7868/ADE7878 Table 49. MMODE Register (Address 0xE700) Bit Location Bit Mnemonic Default Value 1:0 PERSEL[1: PEAKSEL[ PEAKSEL[ PEAKSEL[2] 1 7:5 Reserved 000 Table 50. ACCMODE Register (Address 0xE701) Bit Location Bit Mnemonic Default Value ...
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Table 51. CONSEL[1:0] Bits in Energy Registers Energy Registers CONSEL[1: AWATTHR, AFWATTHR VA × IA BWATTHR, BFWATTHR VB × IB CWATTHR, CFWATTHR VC × IC AVARHR, AFVARHR VA × IA’ BVARHR, BFVARHR VB × IB’ CVARHR, CFVARHR VC ...
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ADE7854/ADE7858/ADE7868/ADE7878 Bit Location Bit Mnemonic Default Value 4:3 HXFER[1: HSAPOL 0 7:6 Reserved 00 Table 54. LPOILVL Register (Address 0xEC00) Bit Location Bit Mnemonic Default Value 2:0 LPOIL[2:0] 111 7:3 LPLINE[4:0] 000 1 The LPOILVL register is available ...
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... ADE7858ACPZ −40°C to +85°C ADE7858ACPZ-RL −40°C to +85°C ADE7868ACPZ −40°C to +85°C ADE7868ACPZ-RL −40°C to +85°C ADE7878ACPZ −40°C to +85°C ADE7878ACPZ-RL −40°C to +85° RoHS Compliant Part. ADE7854/ADE7858/ADE7868/ADE7878 6.10 0.30 6.00 SQ 0.23 5.90 0.18 ...
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ADE7854/ADE7858/ADE7868/ADE7878 NOTES Rev. D| Page ...
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NOTES ADE7854/ADE7858/ADE7868/ADE7878 Rev. D| Page ...
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ADE7854/ADE7858/ADE7868/ADE7878 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08510-0-2/11(D) Rev. D| Page ...