X9530V14I Intersil, X9530V14I Datasheet

IC LASR CTRLR 1CHAN 5.5V 14TSSOP

X9530V14I

Manufacturer Part Number
X9530V14I
Description
IC LASR CTRLR 1CHAN 5.5V 14TSSOP
Manufacturer
Intersil
Type
Laser Diode Controller (Fiber Optic)r
Datasheet

Specifications of X9530V14I

Number Of Channels
1
Voltage - Supply
3 V ~ 5.5 V
Current - Supply
9mA
Operating Temperature
-40°C ~ 100°C
Package / Case
14-TSSOP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X9530V14I
Manufacturer:
Intersil
Quantity:
270
Temperature Compensated Laser Diode
Controller
FEATURES
• Compatible with Popular Fiber Optic Module
• Package
• Two Programmable Current Generators
• Integrated 6 bit A/D Converter
• Temperature Compensation
• Hot Pluggable
• 2176-bit EEPROM
• Write Protection Circuitry
• 3V to 5.5V, Single Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
LASER DIODE BIAS CONTROL APPLICATIONS
• SONET and SDH Transmission Systems
• 1G and 10G Ethernet, and Fibre Channel Laser
PIN CONFIGURATION
Specifications such as Xenpak, SFF, SFP, and
GBIC
—14 Ld TSSOP
—±1.6 mA max.
—8-bit (256 Step) Resolution
—Internal or External Sensor
—-40°C to +100°C Range
—2.2°C/step Resolution
—EEPROM Look-up Tables
—17 Pages
—16 Bytes per Page
—Intersil BlockLock™
—Logic Controlled Protection
—2-wire Bus with 3 Slave Address Bits
Diode Driver Circuits
SDA
SCL
Vcc
WP
A0
A1
A2
TSSOP 14L
1
2
6
3
4
5
7
®
1
14
13
12
11
10
9
8
Data Sheet
I1
I2
VRef
VSense
Vss
R2
R1
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
DESCRIPTION
The X9530 is a highly integrated laser diode bias
controller which incorporates two digitally controlled
Programmable
compensation with dedicated look-up tables, and
supplementary EEPROM array. All functions of the
device are controlled via a 2-wire digital serial interface.
Two temperature compensated Programmable Current
Generators, vary the output current with temperature
according to the contents of the associated nonvolatile
look-up table. The look-up table may be programmed
with arbitrary data by the user, via the 2-wire serial port,
and either an internal or external temperature sensor
may be used to control the output current response.
These
currents maybe used to control the modulation current
and the bias current of a laser diode.
The integrated General Purpose EEPROM is included
for product data storage and can be used for transceiver
module information storage in laser diode applications.
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
X9530V14I*
X9530V14IZ*
(Note)
November 11, 2005
NUMBER
PART
All other trademarks mentioned are the property of their respective owners.
temperature
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
X9530V
X9530V Z
MARKING
PART
Current
Copyright Intersil Americas Inc. 2005. All Rights Reserved
compensated
TEMP RANGE
-40 to 100
-40 to 100
Generators,
(°C)
14 LEAD TSSOP
14 LEAD TSSOP
(Pb-free)
pro-grammable
PACKAGE
X9530
FN8211.1
temperature

Related parts for X9530V14I

X9530V14I Summary of contents

Page 1

... PART PART NUMBER MARKING X9530V14I* X9530V X9530V14IZ* X9530V Z (Note) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

Page 2

... Programmable Current Generators are ideal for use in fiber optic Modulation Current require temperature control. The combination of the X9530 functionality and Intersil’s Chip-Scale package lowers system cost, increases reliability, and reduces board space requirements. Two on-chip Programmable Current Generators may be independently programmed to either sink or source current ...

Page 3

... The resolution is 8 bits. 3 X9530 The EEPROM array is internally organized as 272 x 8 bits with 16-Byte pages, and utilizes Intersil’s proprietary Direct Write™ cells, providing a minimum endurance of 100,000 Page Write cycles and a minimum data retention of 100 years. ...

Page 4

PRINCIPLES OF OPERATION CONTROL AND STATUS REGISTERS The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X9530. The X9530 contains seven Control, one Status, and several Reserved ...

Page 5

Figure 1. Control and Status Register Format Byte MSB Address 6 7 80h I2DS I1DS Non-Volatile I1 and I2 Direction 0: Source 1: Sink Direct Access to LUT1 81h Volatile or Reserved Reserved Non-Volatile Direct Access to LUT2 82h Volatile ...

Page 6

I2DS URRENT ENERATOR IRECTION ( VOLATILE The I2DS bit sets the polarity of Current Generator 2, DAC2. When this bit is set to “0” (default), the Current Generator 2 of the X9530 is ...

Page 7

I2FSO1–I2FSO0 URRENT ENERATOR CALE UTPUT URRENT ET These two bits are used to set the full scale output current at the Current Generator 2 pin, I2. If both bits are set to “0” ...

Page 8

VOLTAGE REFERENCE The voltage reference to the A/D and D/A converters on the X9530, may be driven from the on-chip voltage reference, or from an external source via the VRef pin. Bit VRM in Control Register 0 selects between the ...

Page 9

Figure 4. A/D Converter Input Select Structure ADCIN: bit 3 in Control register 0. VSense Pin On-chip Temperature Sensor VRef A/D Converter Range From Figure 3 we can see that the operating range of the A/D converter input depends on ...

Page 10

Figure 5. D/A Converter Block Diagram VRef Voltage DAC1 or Divider DAC2 Input byte or I2FSO[1:0] bits 1 and and 2 in Control Figure 6. Look-up Table (LUT) Operation LUT2 Row Selection bits D0h LUT1 Row Selection ...

Page 11

By examining the block diagram in Figure 5, we see that the maximum current through pin I1 is set by fixing values for V(VRef) and R1. The output current can then be varied by changing the data byte at the ...

Page 12

D/A Converter 1 Access Summary L1DAS D1DAS Control Source 0 0 A/D converter through LUT1 (Default Bits L1DA5 - L1DA0 through LUT1 X 1 Bits D1DA7 - D1DA0 “X” = Don’t Care Condition (May be either “1” or ...

Page 13

Figure 8. D/A Converter Power-on Reset Response Voltage V ADCOK 0V Current I x 10% x Serial Clock and Data Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH ...

Page 14

Figure 9. Valid Start and Stop Conditions SCL SDA Figure 10. Valid Data Changes on the SDA Bus SCL SDA Figure 11. Acknowledge Response From Receiver SCL from Master SDA Output from Transmitter SDA Output from Receiver START 14 X9530 ...

Page 15

X9530 Memory Map The X9530 contains a 2176 bit array of mixed volatile and nonvolatile memory. This array is split up into four distinct parts, namely: (Refer to Figure 12.) – General Purpose Memory (GPM) – Look-up Table 1 (LUT1) ...

Page 16

Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to Figure 13.). This byte includes three parts: – The four MSBs (SA7 - SA4) are the Device Type Identifier, which must always be ...

Page 17

Figure 15. Byte Write Sequence Signals from the Master Signal at SDA Signals from the Slave Page Write Operation The 2176-bit memory array is physically realized as one contiguous array, organized as 17 pages of 16 bytes each. In order ...

Page 18

Figure 17. Example: Writing 12 bytes to a 16-byte page starting at location 11. 7 bytes Address=0 The four registers Control 1 through 4, have a nonvolatile and a volatile cell for each bit. At power-up, the content of the ...

Page 19

Figure 19. Read Sequence S Slave Signals t Address from the a with Master r R Signal SDA Signals from the Slave The Data Bytes are from the memory location indicated ...

Page 20

... SFF this memory may be used for the storage of transceiver module parameters. input of the laser diode circuit. By loading the or I parameters. The example in Figure PINSET parameter, while PINSET is set at a fixed value using a Intersil Digital of the driver circuit BIASET November 11, 2005 over MON FN8211.1 ...

Page 21

... Figure 20. Typical Laser Driver Circuit Topology High Speed Data Input I MODSET I BIASSET I PINSET Figure 21. X9530 Application Example Block Diagram High Speed Data Input X9530 INTERSIL XDCP MOD_DEF SDA (0) MOD_DEF SCK (1) 21 X9530 Laser Diode Driver Circuit Modulation Currrent Generation I I BIASMAX BIAS Σ ...

Page 22

ABSOLUTE MAXIMUM RATINGS All voltages are referred to Vss. Temperature under bias ................... -65°C to +100°C Storage temperature ........................ -65°C to +150°C Voltage on every pin except Vcc ................ -1.0V to +7V Voltage on Vcc Pin .............................................0 to 5.5V ...................... ...

Page 23

ELECTRICAL CHARACTERISTICS All typical values are for 25°C ambient temperature and pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss unless otherwise specified. All ...

Page 24

D/A CONVERTER CHARACTERISTICS All typical values are for 25°C ambient temperature and pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss unless otherwise specified. ...

Page 25

A/D CONVERTER CHARACTERISTICS All typical values are for 25°C ambient temperature and pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss unless otherwise specified. ...

Page 26

INTERFACE A.C. CHARACTERISTICS Symbol Parameter f SCL Clock Frequency SCL (4) t Pulse width Suppression Time at IN inputs (4) t SCL Low to SDA Data Out Valid AA (4) t Time the bus free before start of new ...

Page 27

TIMING DIAGRAMS Figure 22. Bus Timing t F SCL t SU:DAT t SU:STA t HD:STA SDA IN SDA OUT Figure 23. WP Pin Timing START SCL SDA IN WP Figure 24. Non-Volatile Write Cycle Timing SCL SDA 8th bit of ...

Page 28

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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