PCA9532PW,112 NXP Semiconductors, PCA9532PW,112 Datasheet
PCA9532PW,112
Specifications of PCA9532PW,112
935272837112
PCA9532PW
Related parts for PCA9532PW,112
PCA9532PW,112 Summary of contents
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... To blink LEDs at periods greater than 1.69 second the bus master (MCU, MPU, DSP, chip set, etc.) must send repeated commands to turn the LED on and off as is currently done when using normal I/O expanders like the NXP Semiconductors PCF8575 or PCA9555. Any bits not used for controlling the LEDs can be used for General Purpose ...
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... NXP Semiconductors I Noise filter on SCL/SDA inputs I Active LOW reset input I 16 open-drain outputs directly drive LEDs Controlled edge rates to minimize ground bounce I No glitch on power-up I Supports hot insertion I Low standby current I Operating power supply voltage range 400 kHz clock frequency ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 V Fig 2. Fig 4. PCA9532_4 Product data sheet SDA 3 22 SCL 4 21 RESET 5 20 LED15 6 19 LED14 PCA9532D 7 18 LED13 8 17 LED12 9 16 LED11 10 15 LED10 11 14 LED9 12 13 ...
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... NXP Semiconductors 5.2 Pin description Table 2. Symbol LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 V SS LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 RESET SCL SDA V DD [1] HVQFN24 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board ...
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... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9532 is shown in internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. ...
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... NXP Semiconductors 6.2.1 Control register definition Table 6.3 Register descriptions 6.3.1 INPUT0 - Input register 0 The INPUT0 register reflects the state of the device pins (inputs 0 to 7). Writes to this register will be acknowledged but will have no effect. Table 4. Bit Symbol Default Remark: The default value ‘X’ is determined by the externally applied logic level (normally logic 1) when used for directly driving LED with pull- ...
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... NXP Semiconductors 6.3.3 PCS0 - Frequency Prescaler 0 PSC0 is used to program the period of the PWM output. The period of BLINK0 = (PSC0 + 1) / 152. Table 6. Bit Symbol Default 6.3.4 PWM0 - Pulse Width Modulation 0 The PWM0 register determines the duty cycle of BLINK0. The outputs are LOW (LED on) when the count is less than the value in PWM0 and HIGH (LED off) when it is greater ...
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... NXP Semiconductors 6.3.7 LS0 to LS3 - LED selector registers The LSn LED selector registers determine the source of the LED data output is set high-impedance (LED off; default output is set LOW (LED on output blinks at PWM0 rate 11 = output blinks at PWM1 rate Table 10. Legend: * default value. ...
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... NXP Semiconductors 6.4 Pins used as GPIOs LEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs). For use as input, set LEDn to high-impedance (00) and then read the pin state via the INPUT0 or INPUT1 register. For use as output, connect external pull-up resistor to the pin and size it according to the DC recommended operating characteristics ...
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... NXP Semiconductors 7. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 9. System configuration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 7.4 Bus transactions SCL slave address SDA START condition write to register data out from port Fig 11. Write to register slave address SDA START condition acknowledge slave address (cont (repeated) START condition Fig 12. Read from register slave address SDA START condition ...
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... NXP Semiconductors 8. Application design-in information C-BUS/SMBus MASTER SDA SCL LED0 to LED12 are used as LED drivers. LED13 to LED15 are used as regular GPIOs. Fig 14. Typical application 8.1 Minimizing I When the I/Os are used to control LEDs, they are normally connected to V resistor as shown in I about 1 ...
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... NXP Semiconductors Fig 15. High value resistor in parallel with 8.2 Programming example The following example will show how to set LED0 to LED3 on. It will then set LED4 and LED5 to blink duty cycle. LED6 and LED7 will be set to be dimmed their maximum brightness (duty cycle = 25 %). LED8 to LED15 will be set to off. ...
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... NXP Semiconductors 9. Limiting values Table 12. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I/O I O(LEDn tot T stg T amb PCA9532_4 Product data sheet Limiting values Parameter supply voltage voltage on an input/output pin output current on pin LEDn ground supply current ...
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... NXP Semiconductors 10. Static characteristics Table 13. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb I additional quiescent supply DD current V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...
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... NXP Semiconductors 20 % (1) percent variation (1) maximum (2) average (3) minimum Fig 17. Typical frequency variation over process 2 3 PCA9532_4 Product data sheet 002aac191 20 % percent variation 100 amb (1) maximum (2) average (3) minimum Fig 18. Typical frequency variation over process at Rev. 04 — 17 March 2009 PCA9532 2 16-bit I C-bus LED dimmer ...
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... NXP Semiconductors 11. Dynamic characteristics Table 14. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO ...
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... NXP Semiconductors START SCL SDA RESET 50 % LEDn Fig 19. Definition of RESET timing SDA t BUF t LOW SCL t HD;STA P S Fig 20. Definition of timing PCA9532_4 Product data sheet rec(rst HD;DAT HIGH SU;DAT Rev. 04 — 17 March 2009 PCA9532 2 16-bit I C-bus LED dimmer ACK or read cycle ...
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... NXP Semiconductors protocol SCL SDA Fig 21. I 12. Test information Fig 22. Test circuitry for switching times PCA9532_4 Product data sheet START bit 7 bit 6 condition MSB (A6) (S) (A7 SU;STA LOW HIGH 1 /f SCL t t BUF SU;DAT HD;STA Rise and fall times refer to V and V ...
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... NXP Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 17. Acronym ACPI CDM DSP DUT ESD GPIO HBM 2 I C-bus LED MCU ...
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... Document ID Release date PCA9532_4 20090317 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 5.1 TSSOP24 • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 6 6.3 Register descriptions . . . . . . . . . . . . . . . . . . . . 6 6.3.1 INPUT0 - Input register ...