A3985SLDTR-T Allegro Microsystems Inc, A3985SLDTR-T Datasheet - Page 11

IC MOSFET DRVR PROG DUAL 38TSSOP

A3985SLDTR-T

Manufacturer Part Number
A3985SLDTR-T
Description
IC MOSFET DRVR PROG DUAL 38TSSOP
Manufacturer
Allegro Microsystems Inc
Datasheet

Specifications of A3985SLDTR-T

Configuration
H Bridge
Input Type
Non-Inverting
Delay Time
120ns
Number Of Configurations
2
Number Of Outputs
8
Voltage - Supply
12 V ~ 50 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
38-TSSOP
Device Type
Full Bridge
Module Configuration
Full Bridge
Peak Output Current
500nA
Output Resistance
19ohm
Input Delay
120ns
Output Delay
120ns
Supply Voltage Range
12V To 50V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Peak
-
High Side Voltage - Max (bootstrap)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
620-1180-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3985SLDTR-T
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
A3985
to 0 disables Bridge 1, with all drivers off (see Internal PWM
Current Control, in the Functional Description section).
D7 – Bridge 1 Phase Controls the direction of output cur-
rent for Bridge (load) 1.
D8 – Bridge 1 Mode Determines whether slow decay is
forced or mixed decay, according to Word 1 Bits D3 to D11,
is allowed.
D9 – D14 Bridge 2 Linear DAC These six bits set the
desired current level for Bridge 2. Setting all six bits to 0
disables Bridge 2, with all drivers off (see Internal PWM
Current Control, in the Functional Description section).
D15 – Bridge 2 Phase Controls the direction of output
current for Bridge (load) 2.
D16 – Bridge 2 Mode Determines whether slow decay is
forced or mixed decay, according to Word 1 Bits D3 to D11,
is allowed.
D17 and D18 – G
the range scaling factor, G
according to the following formula:
I
TripDAC
D18
D16
0
0
1
1
D15
m
D8
D7
0
1
0
1
0
1
0
1
Range Select These bits determine
= V
DAC
m
Mixed-decay
Slow-decay
Mixed-decay
Slow-decay
D17
, used in PWM current control,
S1A
S2A
0
1
0
1
H
H
L
L
/ (G
Mode
Mode
m
× R
S1B
S2B
G
12
16
20
H
H
SENSEx
L
L
8
m
)
Dual Full-Bridge MOSFET Driver
Control Register (Word 1) Bit Assignments
This section describes the function of the individual bit val-
ues in the Control register, one of the two registers accessed
through the serial port. The assignments are summarized in
the Bit Assignments table.
Note that the Control register can only be updated when the
WC pin is logic low.
D0 – Register Select Indicates which register should
receive the data. For the Control register, this is set to 1.
D1 and D2 – Blank Time These two bits set the value of
the scaling factor,  / f
the current-sense comparator. The factor for t
because t
D3 through D7 – Fixed Off Time These five bits set the
fixed off-time for the internal PWM control circuitry. Fixed
off-time is defined by:
where n = 0 to 31.
For example, with a master clock frequency of 4 MHz, the
fixed off-time time would be adjustable within the range
1.75 to 63.75 μs, in increments of 2 μs.
D8 through D11 – Fast Decay Time These four bits set
the fast decay portion of fixed off-time for the internal PWM
control circuitry. The fast-decay portion is defined by:
where n = 0 to 15.
For example, with a master clock frequency of 4 MHz, the
fast decay time would be adjustable within the range
1.75 to 32.75 μs, in increments of 2 μs.
DEAD
t
D2
OFF
t
FD
0
0
1
1
= t
= [(1 + n) × 8 / f
= [(1 + n) × (8 / f
Digitally Programmable
BLANK
D1
MCK
0
1
0
1
/ 2 .
, used for determining t
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
12 / f
4 / f
6 / f
8 / f
t
BLANK
MCK
MCK
MCK
MCK
MCK
MCK
)] – 1 / f
)] – 1 / f
(t
BLANK
2 / f
3 / f
4 / f
6 / f
t
DEAD
MCK
MCK
DEAD
MCK
MCK
MCK
MCK
/ 2)
,
,
BLANK
also is set,
for
11

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