TLE6244X Infineon Technologies, TLE6244X Datasheet
TLE6244X
Specifications of TLE6244X
SP000304416
TLE6244
TLE6244
TLE6244XNT
TLE6244XT
TLE6244XXT
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TLE6244X Summary of contents
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... General description 18-fold Low-Side Switch (0.35 ripheral Interface (SPI) and 18 open drain DMOS output stages. The TLE6244X is protected by embedded protection functions and designed for automotive and industrial applications. The output stages are controlled via SPI Interface. Additionally 16 of the 18 channels can be controlled direct in parallel for PWM applications ...
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Description 1.1 Short Description This circuit is available in MQFP64 package or as chip. 1.1.1 Features of the Power Stages Nominal Current R 2.2A OUT1 2.2A OUT3, OUT4 1.1A OUT7, OUT8 2.2A OUT9, OUT10 2.2A OUT11...OUT14 ...
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Block Diagram fault diagnostics IN1 SPI IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 control only via SPI possible control only via SPI possible IN6 IN7 IN16 µsec - Bus SCK SPI ...
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Description of the Power Stages OUT1... OUT6 6 non-inverting low side power switches for nominal currents up to 2.2A. Control is possible by input pins, by the µsec-bus or via SPI. For T below 400m . An integrated zener ...
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All low side switches are equipped with fault diagnostic functions: - short-circuit Batt - short-circuit to ground: (SCG) can be detected if switches are turned off - open load: - overtemperature: The fault conditions SCB, SCG, OL ...
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Pinout Function Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 or FDA Input 7 or SSY Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 or ...
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Supply Voltage VDD Supply Voltage U att B GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 Sense Ground VDD-Monitoring In-/Output VDD-Monitoring Reset (low active) not connected IN15 1 OUT15_1 2 OUT15_2 3 OUT11 4 IN11 5 IN5 6 IN1 7 ...
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Function of Pins IN1 to IN16 Control inputs of the power stages Internal pull-up current sources (exception: IN8 with pull-down current source) FCL Clock for the µsec-bus (pin shared with IN16) FDA Data for the µsec-bus (pin shared with ...
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... TLE6244X always operates in slave mode whereas the controller provides the mas- ter function. The maximum baud rate is 5 MBaud. The TLE6244X is selected by the SPI master by an active slave select signal at SS and by the first two bits of the SPI instruction.SI is the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master ...
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... SS a 17th bit is submitted (SCK=‘1’). After the bits CPAD1,0 and INSTR (4-0) have been sent from the microcontroller TLE6244X is able to check if the instruction code is valid invalid instruction is detected, any modification on a register of TLE6244X is not allowed and the data byte ‘ ...
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... If an invalid instruction is detected bit TRANS_F in the following verification byte is set to ’High’. This bit must not be cleared before it has been sent to the microcontroller TLE6244X and additional IC’s are connected to one common slave select, they are distinguished by the chip address (CPAD1, CPAD0 with 32bit-transmission-format is selected, TLE6232 must not be activated, even if slave select is set to ’ ...
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SPI Instructions SPI Instruction bit 7,6 CPAD1,0 RD_IDENT1 RD_IDENT2 WR_STATCON WR_MUX1 WR_MUX2 WR_SCON1 WR_SCON2 WR_SCON3 WR_CONFIG RD_MUX1 RD_MUX2 RD_SCON1 RD_SCON2 RD_SCON3 RD_STATCON DEL_DIA RD_DIA1 RD_DIA2 RD_DIA3 RD_DIA4 RD_DIA5 RD_CONFIG RD_INP1 RD_INP2 Final Data Sheet Encoding bit 5,4,3,2,1 Parity INSTR(4...0) 00 ...
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Serial/Parallel Control Serial/Parallel Control of the Power Stages 1...16 and Serial Control (SPI) of the Power Stages 17 and 18: The registers MUX_REG1/2 and the bmux-bit prescribe parallel control or serial control (SPI or µsec- bus) of the power ...
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Description of the SPI Registers Register: MUX_REG1 7 6 MUX7 MUX6 State of Reset: 80H Access by Controller: Bit Name 0 MUX0 1 MUX1 2 MUX2 3 MUX3 4 MUX4 5 MUX5 6 MUX6 7 MUX7 Register: MUX_REG2 7 6 ...
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Register: SCON_REG1 7 6 SCON7 SCON6 State of Reset: FFH Access by Controller: Bit Name 0 SCON0 1 SCON1 2 SCON2 3 SCON3 4 SCON4 5 SCON5 6 SCON6 7 SCON7 Register: SCON_REG2 7 6 SCON15 SCON14 State of Reset: ...
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Register: SCON_REG3 State of Reset: FFH Access by Controller: Bit Name 0 SCON16 1 SCON17 7-2 Final Data Sheet Read/Write Description State of serial control of power stage 17 State ...
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Diagnostics/Encoding of Failures Description of the SPI Registers (SPI Instructions: RD_DIA1...5) Register: DIA_REG1 7 6 DIA7 DIA6 State of Reset: FFH Access by Controller: Bit Name 1-0 DIA (1-0) 3-2 DIA (3-2) 5-4 DIA (5-4) 7-6 DIA (7-6) Register: ...
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Register: DIA_REG3 7 6 DIA23 DIA22 State of Reset: FFH Access by Controller: Bit Name 1-0 DIA (17-16) 3-2 DIA (19-18) 5-4 DIA (21-20) 7-6 DIA (23-22) Register: DIA_REG4 7 6 DIA31 DIA30 State of Reset: FFH Access by Controller: ...
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Register: DIA_REG5 State of Reset: FFH Access by Controller: Bit Name 1-0 DIA (33-32) 3-2 DIA (35-34) 4 UBatt 7-5 Encoding of the Diagnostic Bits of the Power Stages DIA(2*x- Final Data ...
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Configuration The µsec-bus is enabled by this register. In addition the shut off at SCB can be configured for the power-stages OUT9, OUT10 and OUT15... OUT18. CONFIG (Read and write O16-SCB O15-SCB State of Reset: FFh Bit ...
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Other Reading the IC Identifier (SPI Instruction: RD_IDENT1): IC Identifier1 (Device ID ID7 ID6 Bit Name 7...0 ID(7...0) Reading the IC revision number (SPI Instruction: RD_IDENT2): IC revision number 7 6 SWR3 SWR2 Bit Name 7...4 SWR(3...0) ...
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Final Data Sheet 22 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 23 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 24 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 25 TLE 6244X V4.2, 2003-08-29 ...
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Final Data Sheet 26 TLE 6244X V4.2, 2003-08-29 ...
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Reading Input1 (SPI Instruction: RD_INP1) : Register INP_REG1 7 6 IN8 Test Bit Name 0..4 IN(1... Test 7 IN8 Reading Input2 (SPI Instruction: RD_INP2): Register INP_REG2 IN15 Bit Name 0..6 IN9...IN15 7 The input pins ...
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Reading the State resp. the Configuration: (SPI Instructions: WR_STATCON, RD_STATCON) Register: STATCON_REG 7 6 CONFIG2 CONFIG1 Bit Name 0 STATUS0 1 STATUS1 2 STATUS2 3 STATUS3 4 STATUS4 5 CONFIG0 Final Data Sheet CONFIG0 STATUS4 STATUS3 Description ...
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CONFIG1 7 CONFIG2 Final Data Sheet Bit = 1: Lower threshold of VDD-monitoring is lifted if bit CONFIG2 = 0 (test of switch-off path) Bit = 0: Upper threshold of VDD-monitoring is reduced if bit CONFIG2 = 0 (test ...
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... OUT9...OUT16 are influenced by the reset input RST. If RST is set to Low, these power stages are switched off. After reset they are controlled by the SPI (default initialization of TLE6244X). Power stage 8 however is not influenced by the reset input if it’s controlled by IN8 and U > ...
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When the bit BMUX in CONFIG is set to Low, the power stages 1...7 and 9...16 are controlled by the µsec-bus-interface on condition that registers MUX_REG1/2 are configured for serial access. The received µsec-bus bit stream (D0... D15) is latched ...
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... Final Data Sheet or has to be switched on by the input pin or via SPI or the UB Voltage regulator U drop U Batt TLE6244X OUTi = (UBR - min drop,max thresOL,max 32 TLE 6244X ...
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Timing Diagram of the Power Outputs 1.9.1 Power Stages U INi U INiH U INiL U OUTi U CLi 0.8U *) CLi U BATT 0.8U BATT 0.2U CLi 0.2U BATT If the output is controlled via SPI the timing ...
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... On undervoltage condition the signal at pin ABE goes high after a filtering time is expired. On overvoltage condition pin ABE goes high either after a filtering time or after a SPI writing instruc- tion. Before this SPI instruction is sent to TLE6244X appropriate tests can be carried out by the controller. If the voltage at pin VDD is below the lower limit or is resp. was above the upper limit, this can be read out by the SPI instruction RD_STATCON ...
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Bit overvoltage at pin VDD 0: overvoltage at pin VDD resp. state of overvoltage still stored Access by controller: read only Testing the VDD-Monitoring: Upper threshold: By writing 000xxxxx b in the register STATCON_REG the overvoltage threshold ...
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Final Data Sheet 100k 36 TLE 6244X <= <= V4.2, 2003-08-29 ...
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Notes for the Application in Commercial Vehicles For electric systems with 24V battery voltage, that can even increase to > _ 37V in case of load dump, some peculiarities have to be observed! The static voltage at pin UBatt ...
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Notes for the Diagnostics - SCB entry in DIA_REGx see diagrams in chapter 1.6. case of overvoltage at pin VDD (VDD > 5,5V) the diagnostic information can be wrong. In that case, the diagnostic information has to ...
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State Diagram of the Power Stages Diagnostics Final Data Sheet 39 TLE 6244X V4.2, 2003-08-29 ...
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... I , see page 36, 37). GND Max. number of parallel connections: 3 The following statements apply to PS within the same TLE6244X The max. short circuit shutdown threshold of the parallel connected PS is the summation of the corre- sponding max. values of the PS (I Max. Nominal Current 2 symmetrical PS 0 ...
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... PS is the summation of the corresponding max. values of the +....). SC,OUTx SC,OUTy The following statements apply to Power Stages within different TLE6244X The application has to take into account that all maximum ratings of each TLE6244X are observed. Final Data Sheet 41 TLE 6244X V4.2, 2003-08-29 ...
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Maximum Ratings 2.1 Definition of Test Conditions The integrated circuit must not be destroyed if maximum ratings are reached. Every maximum rating is allowed to reach, as far as no other maximum rating is exceeded. Unless otherwise indicated all ...
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Output current Outputs Low Side Switches Static voltage (without destruction) OUT1...6 Dynamic voltage without destruction after ISO/DIS7637-1, pulses OUT1 to 6, OUT9 to16: via external load (e.g. 2W lamp) OUT7, OUT8, OUT17 and OUT18: via external load ...
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Electrical Characteristics 3.1 Operating Out of this range the power stages Range can be shut off by the VDD-moni- (see also 3.13 toring except OUT8 VDD-monitoring ABE) Voltage referred to GND_ABE Minimum reset duration (Power-On) Minimum reset duration in ...
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Power Con- U VDD sumption 5,5 V < UVDD < (IC is not destroyed) U UBatt = 14V U UBatt = 28V U UBatt Power consumption in standby mode in case of missing U VDD, U UBatt ...
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Input Protec- Input clamping at INi (i = 1...16): tion INi No malfunction during clamping. Max. clamping current (externally limited) static dynamic (t < 2ms) Max. clamping voltage I = -5mA INi I = +2mA (t < 2ms) INi ...
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Between -40°C and 150°C an approximately linear characteristic line can be assumed for the short circuit shutdown threshold. Between 17V short circuit shutdown threshold is switched. A power stage that is switched off in case of SCB can be switched ...
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Leakage Cur- U VDD rent age current of the DMOS, diag- nostic current = 0) U VDD age current of the DMOS, diag- nostic current = 0) 3.5.8 Clamping 3.5.8.1 Clamping I OUT1...6 Voltage 3.5.8.2 Matching of Between different ...
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Power outputs In case of open input (parallel con- 2.2A/45V trol) or missing power supply the OUT9...OUT14 power stage is switched off. Paral- lel connection of power stages is possible. 3.6.1 Nominal Cur- rent 3.6.2 Extended Cur- I > ...
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A power stage that is switched off in case of SCB can be switched on again by an off/on cycle at the cor- responding input pin resp. by the change of the state of the corre- sponding bit for SPI ...
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On /off Delay „On“ Times „Off“ (Measurement with ohmic load don switch-on slew rate switch-off slew rate 3.6.7 Leakage Cur- U VDD rent (leakage current of the DMOS, diagnostic current = 0) U VDD (leakage current ...
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Power outputs In case of open input (parallel con- 3.0A/45V trol) or missing power supply the OUT15...OUT16 power stage is switched off. Paral- lel connection of power stages is possible. 3.7.1 Nominal Cur- rent 3.7.2 Extended Cur- I OUT15,16 ...
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On Resis 25°C: J tance T = 150° -40°C: J For U UBatt up to 20%. 3.7.6 On /off Delay „On“ Times „Off“ (Measurement with ohmic load don switch-on slew rate ...
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Maximum For a maximum of 10 times during Clamping En- ECU life (load dump with 400ms ergy at Load and R Dump lamp) 3.7.8.6 Jump Start Each output 150% of the values of 3.7.8.3. For a maximum of 10 ...
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Between -40°C and 150°C an approximately linear characteristic line can be assumed. Between 17V short circuit shutdown threshold is switched for OUT7/8 A power stage that is switched off in case of SCB can be switched on again by an ...
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On Resis 25°C J tance T = 150° -40°C J For U UBatt 10V increased up to 20%; condition: U VDD > 4.5 V For OUT8 only: 3.5V<(U VDD , U ...
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Maximum Each output 75% of the values of Clamping En- 3.8.8.2 resp. 3.8.8.3. ergy with two Outputs con- nected in par- allel 3.8.8.5 Maximum For a maximum of 10 times during Clamping En- ECU life (load dump with 400ms ...
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... SPI Interface The timing of TLE6244X is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is sampled on the falling edge of the SCK signal. - The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal, if exactly 16 SPI clocks have been counted during SS = active ...
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... SPI data input 3.9.3.1 Low Level 3.9.3.2 High Level 3.9.3.3 Hysteresis 3.9.3.4 Input Capaci- ty 3.9.3.5 Input Current Pull up current source connected to VDD 3.9.4 Output SO Tristate output of the TLE6244X (SPI output); On active reset (RST) output tristate. 3.9.4.1 Low Level I = 2mA SO 3.9.4.2 High Level I ...
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... Data Valid CL = 50pF (5 MHz) Data Valid CL = 200pF (2MHz) (referred to TLE6244X) 5. Data Setup Time (referred to master) 6. Data Hold Time (referred to master) 7. Disable Time (referred to TLE6244X) 8. Transfer Delay (referred to master) 9. Select time (referred to master) 10. Access time (referred to master) 11. Serial clock high time (referred to master) 12 ...
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... The clock signal may remain on high or low statically during SSY = high. A rising edge at SSY and a falling edge at FCL must not occur simultaneously! On the rising edge of SSY the 16 bits clocked in TLE6244X by the last 16 falling edges at FCL are latched. 3.10.1 Input FCL, µsec-bus interface pins FDA, SSY 3 ...
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Switching time on FCL f FCL > 10MHz Select hold time FCL Low time FCL High time SSY Low time SSY High time Time between rising edge of SSY and next falling edge of FCL 3.11 Diagnostics 3.11.1 Diagnostic Thresholds ...
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Filtering Time from occurrence of one of Time Power the errors ’short to ground’, ’open Switches load’ or ’short to battery’ until the fault is entered into the corre- sponding diagnostic register. Time from occurrence of OT until the ...
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VDD-Monitor- Bidirectional: open drain output / ing ABE input with pull up current source An external current limitation must guarantee I ABE < for any U ABE 3.13.1 Output U ABE 2.7V < U 5.3V... 5.5V < ...
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Undervolt- Voltage referred to GND_ABE age Thresh- old 3.13.5 Test Mode: Voltage referred to GND_ABE Reducing the Overvoltage Threshold 3.13.6 Test Mode: Voltage referred to GND_ABE Lifting the Undervoltage Threshold 3.13.7 Suppres- Periodical alternating between sion of overvoltage and ...
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Clamping Energy 3.14 f(I ), 2.2A Power Stages with 70V Clamping OUT1... 3.14 2.2A Power Stages with 45V Clamping OUT9...A14 ...
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E = f(I ), 1100mA Power Stages with 45V Clamping OUT7,8,17, 3.14 f(I ), 3.0A Power Stages with 45V Clamping OUT15, OUT16 ...
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ESD All pins of the IC have to be protected against electrostatic discharge (ESD) by appropriate pro- tection components. The integrated circuit has to meet the requirements of the „Human Body Model“ with 100pF and R2 ...
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Package Outline Final Data Sheet 69 TLE 6244X V4.2, 2003-08-29 ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...