IRMCK311TR International Rectifier, IRMCK311TR Datasheet
IRMCK311TR
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IRMCK311TR Summary of contents
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Dual Channel Sensorless Motor Control IC for Features TM MCE (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Integrated Power Factor Correction control Supports both interior and surface permanent ...
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... SPI Read AC Timing.................................................................................................... 24 7.9 UART AC Timing .............................................................................................................. 25 7.10 CAPTURE Input AC Timing .......................................................................................... 26 7.11 JTAG AC Timing ............................................................................................................ 27 7.12 OTP Programming Timing .............................................................................................. 28 8 I/O Structure .............................................................................................................................. 29 9 Pin List....................................................................................................................................... 32 10 Package Dimensions............................................................................................................... 35 11 Part Marking Information....................................................................................................... 36 12 Ordering Information ............................................................................................................. 36 www.irf.com TABLE OF CONTENTS 2 IRMCK311 © 2007 International Rectifier ...
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... Figure 21 Analog input......................................................................................................30 Figure 22 Analog operational amplifier output and AREF I/O structure..........................30 Figure 23 VPP programming pin I/O structure .............................................................30 Figure 24 VSS and AVSS pin structure ............................................................................31 Figure 25 VDD1 and VDDCAP pin structure ....................................................................31 Figure 26 XTAL0/XTAL1 pins structure..........................................................................31 www.irf.com TABLE OF FIGURES 3 IRMCK311 © 2007 International Rectifier ...
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... Table 12. GATEKILL to SVPWM AC Timing ............................................................................ 21 Table 13. Interrupt AC Timing...................................................................................................... 21 2 Table 14 Timing .............................................................................................................. 22 Table 15. SPI Write AC Timing.................................................................................................... 23 Table 16. SPI Read AC Timing..................................................................................................... 24 Table 17. UART AC Timing......................................................................................................... 25 Table 18. CAPTURE AC Timing ................................................................................................. 26 Table 19. JTAG AC Timing.......................................................................................................... 27 Table 20. OTP Programming Timing............................................................................................ 28 Table 21. Pin List .......................................................................................................................... 32 www.irf.com TABLE OF TABLES 4 IRMCK311 © 2007 International Rectifier ...
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... Overview IRMCK311 is a new International Rectifier integrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance dual motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK311 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCE ...
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... IRMCK311 contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCE o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transition www.irf.com IRMCK311 © 2007 International Rectifier ...
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... Therefore only 56K byte OTP memory area is usable for 8051 microcontroller. Note 2: Total size of RAM is 8K byte including MCE program, MCE data, and 8051 data. Different sizes can be allocated depending on applications. www.irf.com program One-Time Programmable memory Note 2 7 IRMCK311 Note 1 © 2007 International Rectifier ...
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... P1.3/SYNC/SCK 5 P1.4/CAP 6 VDD2 7 VSS 8 VDD1 9 FGATEKILL 10 FPWMWL 11 FPWMWH 12 FPWMVL 13 FPWMVH 14 FPWMUL 15 FPWMUH www.irf.com (Top View) Figure 3. IRMCK311 Pin Configuration 8 IRMCK311 48 P3.0/INT2/CS1 47 CPWMUH 46 CPWMUL CPWMVH 45 CPWMVL 44 43 CPWMWH 42 CPWMWL 41 CGATEKILL 40 VDD1 VSS 39 IPFC IPFC+ 36 IPFCO 35 VACO 34 VAC- VAC+ 33 © 2007 International Rectifier ...
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... Input/Output of IRMCK311 All I/O signals of IRMCK311 are shown in Figure 4. All I/O pins are 3.3V logic interface except A/D interface pins. www.irf.com Figure 4. Input/Output of IRMCK311 9 IRMCK311 © 2007 International Rectifier ...
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... Output, motor 2 PWM phase U high side gate signal FPWMUL Output, motor 2 PWM phase U low side gate signal www.irf.com nd channel Receive data to IRMCK311, can be configured as P3.6 nd channel Transmit data from IRMCK311, can be configured clock output, SPI SO- Data line, Chip Select 0 of SPI 10 IRMCK311 © 2007 International Rectifier ...
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... Input/Output, Analog input channel 0 or Operational amplifier output for DC bus voltage sensing AIN1 Input, Analog input channel 1 (0-1.2V), needs to be pulled down to AVSS if unused 4.4 Power Interface Group VDD1 Digital power for I/O (3.3V) VDD2 Digital power for core logic (1.8V) www.irf.com 11 IRMCK311 © 2007 International Rectifier ...
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... SCL/SO-SI/VPP OTP programming supply. Can be left open in OTP read mode (normal) 4.5 Test Interface P5.3/TDI Input, JTAG test data input P5.1/TMS Input, JTAG test mode select TCK Input, JTAG test clock P5.2/TDO Output, JTAG test data output www.irf.com 12 IRMCK311 © 2007 International Rectifier ...
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... DC bus shunt IFBF- IFBFO 0.6V IPFC+ IPFC- IPFCO VAC+ VAC- VACO DC bus AIN0 voltage AIN1 Other analog input (0-1.2V) AREF Optional External Voltage Reference (0.6V) CMEXT AVDD(1.8V) AVSS © 2007 International Rectifier FAN motor resistor PFC DC bus shunt resistor AC line voltage ...
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... Power Consumption 1.8V 3.3V Total Power MCE Frequency (MHz) 14 IRMCK311 Max Condition 3.6 V Respect to VSS 1.98 V Respect to VSS 7.0V Respect to VSS 1.98 V Respect to AVSS 3.65 V Respect to VSS 85 ˚C 150 ˚C Max Unit 128 MHz 32 MHz 100 120 140 © 2007 International Rectifier ...
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... V 1 PLLVSS 0.8* V PLLVDD Table 4. PLL DC Characteristics 15 IRMCK311 Max Condition 3.6 V Recommended 1.98 V Recommended 7.0V Recommended 0.8 V Recommended 3.6 V Recommended (1) - ±1 μ ( (1) Max Condition 1.92 V Recommended 0. 1.8 V PLLVDD (1) V PLLVDD 1.8 V PLLVDD PLLVDD (1) © 2007 International Rectifier ...
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... Min Typ 1. ( kΩ 100 μA Table 5. Analog I/O DC Characteristics 16 IRMCK311 Max Condition 1.89 V Recommended 1.8 V AVDD 1.2 V Recommended 1 1.8 V AVDD (1) - Requested 20 kΩ between op amp output and negative input ( 0.6 V OUT ( 0.6 V OUT (1) © 2007 International Rectifier ...
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Under Voltage Lockout DC Characteristics - Based on AVDD (1.8V) Unless specified 25˚C. Symbol Parameter UV UVcc positive going CC+ 1) Threshold UV UVcc negative going CC- Threshold UV H UVcc Hysteresys CC Note: 1) Data guaranteed ...
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... MHz 4 MHz 32 MHz 50 MHz F ÷ 256 - CLKIN - 200 psec - Table 8. PLL AC Characteristics R = =10 Xtal 2 C =30PF 1 C =30PF 2 Figure 7 Crystal oscillator circuit 18 IRMCK311 Max Condition (1) 60 MHz (see figure below) (1) 128 MHz (1) - (1) - (1) - (1) 500 μsec © 2007 International Rectifier ...
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... Data guaranteed by design. www.irf.com . Min Typ - - - - Voltage droop t SAMPLE T HOLD Min Typ - 10 V/μsec Ω - 400 ns 19 IRMCK311 Max Condition (1) 2.05 μsec 10 μsec Voltage droop ≤ 15 LSB (see figure below) S/H Voltage Max Condition - AVDD ( ( 1 AVDD ( © 2007 International Rectifier ...
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... SYNC to PWM output dSYNC3 delay time Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events www.irf.com t wSYNC t dSYNC1 t dSYNC2 t dSYNC3 Min Typ - Table 11. SYNC AC Characteristics 20 IRMCK311 Max Unit - SYSCLK 100 SYSCLK 200 SYSCLK (1) 2 SYSCLK © 2007 International Rectifier ...
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... Interrupt AC Timing Unless specified 25˚C. Symbol Parameter t INT0, INT1 Interrupt wINT Assertion Time t INT0, INT1 latency dINT www.irf.com Min Typ Figure 11 Interrupt AC Timing Min Typ Table 13. Interrupt AC Timing 21 IRMCK311 Max Unit - SYSCLK 100 SYSCLK Max Unit - SYSCLK 4 SYSCLK © 2007 International Rectifier ...
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... C read setup time is determined by the programmable filter time applied to I communication. www.irf.com T T I2CLK I2CLK I2WSETUP I2WHOLD I2RSETUP 2 Figure Timing Min Typ 10 0.25 0.25 0.25 0. filter time 1 2 Table 14 Timing 22 IRMCK311 t I2EN1 t I2RHOLD t I2EN2 Max Unit - 8192 SYSCLK - - T I2CLK - - T I2CLK - - T I2CLK - - T I2CLK - - SYSCLK - - SYSCLK 2 C © 2007 International Rectifier ...
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... WRDELAY delay time t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 13 SPI AC Timing Min Typ 1 Table 15. SPI Write AC Timing 23 IRMCK311 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec 10 nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
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... RDHOLD t CS high time between two CSHIGH consecutive byte transfer t CS hold time CSHOLD www.irf.com Figure 14 SPI Read AC Timing Min Typ 1 Table 16. SPI Read AC Timing 24 IRMCK311 Max Unit - SYSCLK - T SPICLK - T SPICLK 10 nsec - nsec - nsec - T SPICLK - T SPICLK © 2007 International Rectifier ...
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... Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/ three sampled values do not agree, then UART noise error is generated. BAUD www.irf.com Data and Parity Bit Stop Bit T UARTFIL Figure 15 UART AC Timing Min Typ - 57600 - 1/16 Table 17. UART AC Timing 25 IRMCK311 Max Unit - bit/sec - T BAUD © 2007 International Rectifier ...
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... CAPTURE rising edge CLDELAY to capture register latch time t CAPTURE input INTDELAY interrupt latency time www.irf.com Figure 16 CAPTURE Input AC Timing Min Typ Table 18. CAPTURE AC Timing 26 IRMCK311 Max Unit - SYSCLK - SYSCLK - SYSCLK 4 SYSCLK 4 SYSCLK 4 SYSCLK © 2007 International Rectifier ...
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... JHIGH t TCK Low Period JLOW t TCK to TDO propagation CO delay time t TDI/TMS setup time JSETUP t TDI/TMS hold time JHOLD www.irf.com t JHOLD Figure 17 JTAG AC Timing Min - Table 19. JTAG AC Timing 27 IRMCK311 Typ Max Unit - 50 MHz - - nsec - - nsec - 5 nsec - - nsec - - nsec © 2007 International Rectifier ...
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... OTP Programming Timing Unless specified 25˚C. Symbol Parameter T VPP Setup Time VPS T VPP Hold Time VPH www.irf.com Figure 18 OTP Programming Timing Min 10 15 Table 20. OTP Programming Timing 28 IRMCK311 Typ Max Unit - - nsec - - nsec © 2007 International Rectifier ...
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... The following figure shows the motor PWM and digital I/O structure except the motor PWM output Figure 19 All digital I/O except motor PWM output The following figure shows RESET and GATEKILL I/O structure. www.irf.com Figure 20 RESET, GATEKILL I/O 29 IRMCK311 © 2007 International Rectifier ...
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... Figure 23 VPP programming pin I/O structure The following figure shows the VSS, AVSS and PLLVSS pin structure www.irf.com AVDD Analog input 6.0V PIN 100 Analog Circuit 6.0V AVSS Figure 21 Analog input 1.8V Analog output 6.0V PIN Analog Circuit 6.0V AVSS 30 IRMCK311 © 2007 International Rectifier ...
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... The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure Figure 25 VDD1, VDD2, AVDD and PLLVDD pin structure The following figure shows the XTAL0 and XTAL1 pins structure www.irf.com PIN 6.0V VSS Figure 26 XTAL0/XTAL1 pins structure 31 IRMCK311 © 2007 International Rectifier ...
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... Analog input channel 0, 0-1.2V range, needs to be pulled down to AVSS if unused P 1.8V analog power P Analog common I Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused O Analog reference voltage output (0.6V) O Unbuffered analog reference voltage output (0.6V) 32 IRMCK311 © 2007 International Rectifier ...
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... Discrete programmable I/O or INT0 input I/O Discrete programmable I input I/O Discrete programmable I output P Digital common 2 I clock output or SPI data or OTP programming P voltage 2 I data or SPI chip select 0 I/O Discrete programmable I/O or JTAG test mode select 33 IRMCK311 nd UART receive nd UART transmit © 2007 International Rectifier ...
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... I/O Discrete programmable I/O or JTAG port test data output I/O Discrete programmable I/O or JTAG test data input I JTAG test clock - No connection I/O Reset , low true, Schmitt trigger input P 1.8 V PLL power P PLL ground Table 21. Pin List 34 IRMCK311 © 2007 International Rectifier ...
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... Package Dimensions www.irf.com © 2007 International Rectifier 35 IRMCK311 ...
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... This product has been designed and qualified for the industrial level Qualification standards can be found at IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 12/25/2007 36 IRMCK311 The LQFP-100 is MSL3 qualified www.irf.com <http://www.irf.com> © 2007 International Rectifier ...