ICE1QS01G Infineon Technologies, ICE1QS01G Datasheet - Page 11

• Manufacturer Part Number: ICE1QS01G
• Description: IC PFC CONTROLLER DSO8
• Manufacturer: Infineon Technologies

Specifications of ICE1QS01G

• Current - Startup: 60µA
• Voltage - Supply: 9 V ~ 20 V
• Operating Temperature: -25°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Switching: -
• Mode: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: SP000081002

SRC (Regulation and soft start capacitor)
The feedback capacitor is connected to pin SRC. The feedback voltage V
tions.
Function I (MOS FET on time): V
tains the primary current information) exceeds the V
switched off.
Function II (MOS FET off time for frequency reduction): At low load the frequency is reduced by
ignoring zero crossing signals after the transformer demagnetization. V
the 4-bit up-down-counter which contains the number of zero crossings to be ignored. The content
of the up-down-counter is compared with the number of zero-current crossings of V
number of zero-current crossings in each period after the transformer demagnetization is equal to
the up-down-counter content the MOS is switched on. At low load conditions when V
3.5V the counter is increased by one every 50 msec. The result is that the MOS transistor off-time
increases and duty cycle decreases. At high load conditions when V
counter content is reduced by one every 50msec. So MOS transistor off-time will be reduced. With
this off-time regulation switching jitter can be eliminated.
The up-down-counter is immediately set to 0001 if a load jump occurs and V
This ensures that full power can be provided instantaneously.
The following table shows the SRC voltage range and the corresponding up-down counter action.
The information provided by V
trigger pulse with a period of 50 msec. Every time the pulse occures the up-down counter checks
the status flip flops and acts depending on the flip flop information. After this pulse the flip flops are
reset. So change of voltage range is noticed by the logic only once during the 50 ms period. In the
diagram below the behaviour of the up-down counter is depicted in more detail.
Version 1.4
SRC voltage range
1: VSRC< 3.5V
2: 3.5<VSRC<4.4
3: VSRC>4.4
4: VSRC> 4.8
tim e r p u ls e tp
V S R C
D ia g r a m 1
u p - d o w n
s ta tu s o f
c o u n te r
4 .5 V
3 .5 V
n
n + 1
tp
5 0 m s e c
SRC
up-down-counter action
count forward
stop count
count backward
set up-down-counter to1
n + 1
SRC
tp
is stored in two independent flip flops. An internal timer creates a
provides the switch off reference voltage. If V
n + 1
tp
11
n + 1
tp
SRC
n + 1
tp
voltage the external MOS transistor is
n
tp
SRC
SRC
SRC
determines the action of
n - 1
is higher than 4.4V the
tp
SRC
has two main func-
PCS
exceeds 4.8 V.
n - 2
tp
ICE1QS01
SRC
(which con-
27 Apr 2004
RZI.
is below
n - 3
If the
tp