ICE1CS02G Infineon Technologies, ICE1CS02G Datasheet - Page 12

• Manufacturer Part Number: ICE1CS02G
• Description: IC PFC CTRLR AVERAGE CURR DSO16
• Manufacturer: Infineon Technologies

Specifications of ICE1CS02G

• Mode: Average Current
• Frequency - Switching: 65kHz
• Current - Startup: 1.3mA
• Voltage - Supply: 11 V ~ 25 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000444092; SP000783614

Figure 11
3.4.6
Whenever VSENSE voltage falls below 0.6V, or
equivalently V
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.6V as shown in the
IC block diagram in Figure 2.
3.4.7
Whenever V
OVP), higher than 3.15V, the over-voltage protection
OVP is active as shown in Figure 8, turning off gate. In
addition, a VSENSE voltage higher than 3.15V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage V
Version 1.0
Full-wave
Rectifier
I
R1
INDUCTOR
ISENSE
R2
Open Loop Protection / Input Under
Voltage Protect (OLP)
Over-Voltage Protection (OVP)
Peak Current Limit (PCL)
OUT
OUT
exceeds the value set by pin 3 (PFC
falls below 20% of its rated value, it
Current Limit
1.43x
1.0V
O P 1
C 2
OUT
Turn Off
Driver
.
IN
for
12
3.4.8
The complete system current loop is shown in Figure
13.
Figure 12
It consists of the current loop block which averages the
voltage at pin 16 (PFC ISENSE), resulted from the
inductor current flowing across R1. The averaged
waveform is compared with an internal ramp in the
ramp generator and PWM block. Once the ramp
crosses the average waveform, the comparator C1
turns on the driver stage through the PWM logic block.
The Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
3.4.9
The compensation of the current loop is done at the pin
1 (PFC ICOMP). This is the OTA2 output and a
capacitor C3 has to be installed at this node to ground
(see Figure 13). Under normal mode of operation, this
pin gives a voltage which is proportional to the
averaged inductor current. This pin is internally shorted
to 4V in the event of IC shuts down when OLP and
UVLO occur.
3.4.10
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D
CCM PFC system is given as
From the above equation, D
D
OFF
C3
ISENSE
ICOMP
=
PFC
PFC
------------- -
V
V
R2
OUT
Combi PFC/ PWM Controller
IN
Full-wave
Complete Current Loop
Complete System Current Loop
Current Loop Compensation
Pulse Width Modulation (PWM)
Retifier
From
R1
Current Loop
1.0mS
+/-50uA (linear range)
Compensation
Current Loop
Fault
S2
OTA2
L1
Functional Description
4V
R7
OFF
Inductor current
proportional to
is proportional to V
Comparator
averaged
voltage
PWM
D1
Nonlinear
C1
Gain
ICE1CS02
25 July 2008
C2
GATE
Driver
Gate
PWM Logic
R
S
R3
Voltage Loop
R4
Input From
OFF
Q
Vout
for a
IN
.